Stefan Rave

To cope with the enhanced luminosity delivered by the Large Hadron Collider from 2021 onwards, the ATLAS experiment has planned several upgrades.The first level trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature EXtractors (FEXs, FPGA-based trigger boards), each optimized to trigger on different physics objects.This contribution is focused on the jet FEX.The main challenges of such a board are the input bandwidth of up to 3.1 Tbps, dense routing of high-speed signals and power consumption.The design, PCB simulations and results of integrated tests of a prototype are shown in this document.

To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. This requires the use of large Field Programmable Gate Array (FPGA) with the largest number of Multi Gigabit Transceiver (MGT) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signal board. MEGTRON6 was chosen as the material for the 24 layers jFEX board stack-up because of its property of low transmission loss with high frequency signals (GHz range) and to further preserve the signal integrity special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. An integrated test has been installed at the ATLAS test facility to perform numerous tests and measurements with the jFEX prototype.

The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate into the use of large Field Programmable Gate Array (FPGA) with the largest number of Multi Gigabit Transceivers (MGTs) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signal board. MEGTRON6 was chosen as the material for the 24 layers jFEX board stack-up because of its property of low transmission loss for high frequency signals (GHz range) and to further preserve the signal integrity special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. The jFEX prototype was delivered at the beginning of December and the preliminary results on the design validation and board characterisation will be reported.

The ‘Phase-I’ upgrade of the Large Hadron Collider (LHC), scheduled to be completed in 2021, will lead to an enhanced collision luminosity and an increased number of interactions per LHC bunch crossing. To cope with the new and challenging accelerator conditions, all the CERN experiments have planned a major detector upgrade to be installed during the associated experimental shutdown period. One of the physics goals of the ATLAS experiment is to maintain sensitivity to electroweak processes despite the increased event rate. To this end, the first-level hardware trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature EXtractors (FEXs), which each uses different physics objects for trigger selection. There will be three FEX systems in total, the electron, the jet and the global Feature Extractor. This contribution focuses on the first prototype of the jet FEX (jFEX) and presents the hardware design challenges and adopted solutions to preserve signal integrity within a densely populated high signal speed ATCA board.

To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of ~3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without affecting the main board. The 24-layers stack-up was carefully designed to preserve the signal integrity in a very densely populated high speed signal board selecting MEGTRON6 as the most suitable PCB material. This contribution reports on the design challenges and the test results of the jFEX prototypes. In particular the fully assembled final prototype has been tested up to 12.8 Gb/s in house and in integrated tests at CERN. The full jFEX system will be produced by the end of 2018 to allow for installation and commissioning to be completed before LHC restarts in March 2021.

To cope with the expected increase in luminosity at the Large Hadron Collider in 2021, the ATLAS collaboration is planning a major detector upgrade to be installed during Long Shutdown 2. As a part of this, the Level-1 trigger based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEXs), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) has been conceived to identify small/large area jets, large area tau leptons, missing transverse energy and the total sum of the transverse energy. The use of the latest generation Xilinx field programmable gate array (FPGA), the Ultrascale+, was dictated by the physics requirements which include substantial processing power and large input bandwidth, up to ~ 3Tb/s, within a tight latency budget of less than 390 ns. The modular design of the jFEX board allowed for an optimal routing of a large number of high speed signals within the limited space of an ATCA board. To guarantee the signal integrity, the board design has been accompanied by simulation of the power, current and thermal distribution. The printed circuit board has a 24-layer stack-up and uses the MEGTRON6 material, commonly used for signal transmission above 10 Gb/s. The jFEX system, consisting of 6 boards, will be produced by the end of 2018 to allow the installation and commissioning of the full system in time for the LHC restart at the beginning of 2021.

After the Long Shutdown 2 (Dec.2018 -Feb.2021), the LHC will be a new machine in many respects and produce collisions with a center-of-mass energy at or near 14 TeV.The instantaneous luminosities can be expected to reach 2 × 10 34 cm -2 s -1 , which is two times the original design value.The mean number of interactions per bunch crossing is expected to go up to 80.To meet the challenges of the high-luminosity environment (much higher event rates and pileup level), several major upgrades will be installed during the Long Shutdown 2 in the ATLAS detector.As a part of the updates, the Level-1 calorimeter trigger will be upgraded to exploit higher granularity data compared to those available during Run 2 by using a new system of feature extraction modules, which each reconstructs different physics objects at Level-1.The Jet Feature Extractor (jFEX) is one of three feature extraction modules and has been conceived to identify small-/large-area jets, large-area τ leptons, missing transverse energy and the total sum of the transverse energy.The Xilinx Virtex UltraScale+ FPGA fulfills the physics requirements of significant processing power and large input bandwidth within a tight latency budget.The modular design optimizes a large number of high-speed signals within the limited space of an ATCA board.To guarantee the signal integrity, the board design has been accompanied by simulation of the power, current, and thermal distributions.The printed circuit board has a 24-layer stack-up and uses the MEGTRON6 material, which is commonly used for signal transmission above 10 Gb/s.This contribution focuses on the technological aspects of the jFEX module, reporting on the simulation studies and the design solutions of the board.Two jFEX prototypes and one pre-production module have been produced and tested at CERN with other systems, and these test results are presented.The firmware implemented on the trigger board will be illustrated in connection with the FPGA performance and board power consumption.The whole jFEX system, consisting of 6 boards, will be produced by the end of 2019 to allow the installation and commissioning of the full system in time for the LHC restart at the beginning of 2021.