S. Stärz

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation in the high-luminosity phase of the LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming detector signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

Abstract The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the high luminosity phases of LHC will be increased by factors of 3–7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background rejection rates. The general concept of the upgraded LAr calorimeter readout together with the various electronics components to be developed for such a complex system is presented. The R&D activities and architectural studies undertaken by the ATLAS LAr Calorimeter group are described.

The Liquid Argon calorimeter of the ATLAS detector at CERN near Geneva is equipped with improved readout and trigger electronics for the operation at higher luminosity LHC in the frame of several upgrades (Phase-0, I, and II). Special attention is given to an early digitisation of detector raw data and their following digital data transmission and processing via FPGAs already for the Level-1 trigger. The upgrades additionally foresee to provide higher spatial granularity information for the Level-1 trigger in order to improve its performance for low momentum single particles at increased collision rates. The first part of this dissertation contains the development and implementation of a modular detector simulation framework, AREUS, which allows to analyse different filter algorithms for the energy reconstruction as well as their performance with respect to the expected digitised detector raw data. In this detector simulation framework the detailed algorithmic functionality of the FPGAs has been taken into account. Various filter algorithms, especially the Optimal Filter and a Wiener Filter with Forward Correction, are discussed with regard to their performance in energy reconstruction of the future Liquid Argon calorimeter trigger system. In the second part of this thesis, the high-speed data transfer for the acquisition of the trigger data is being developed. For this purpose, a generic 10 Gigabit Ethernet UDP stack is designed in VHDL, that is currently applied in an ALTERA® Stratix-IV FPGA as part of the readout electronics of a demonstrator setup in the context of the Phase-0 Upgrade. After implementation in a prototype electronics board, data transfer from the detector front-end is realised. A successful test in the demonstrator setup installed in the ATLAS detector verifying the correct transmission of the Liquid Argon calorimeter trigger signals concludes this work.

A new readout driver (ROD) is being developed as a central part of the signal processing of the ATLAS liquid-argon calorimeters for operation at the High Luminosity LHC (HL-LHC). In the architecture of the upgraded readout system, the ROD modules will have several challenging tasks: receiving of up to 1.4 Tb/s of data per board from the detector front-end on multiple high-speed serial links, low-latency data processing, data buffering, and data transmission to the ATLAS trigger and DAQ systems. In order to evaluate the different components, prototype boards in ATCA format equipped with modern Xilinx and Altera FPGAs have been built. We will report on the measured performance of the SERDES devices, the parallel signal processing using DSP slices, the implementation of trigger interfaces, using e.g. multi-Gb Ethernet, as well as the development of the ATCA infrastructure on the very first ROD prototype modules.

The ATLAS detector was designed and built to study proton-proton collisions produced at the LHC at centre-of-mass energies up to 14 TeV and instantaneous luminosities up to $10^{34} \mathrm{cm}^{-2} \mathrm{s}^{-1}$. A liquid argon sampling calorimeter (LAr) is employed as electromagnetic calorimeter and hadronic calorimeter, except in the barrel region, where a scintillator-steel sampling calorimeter (TileCal) is used for the hadronic calorimeter. ATLAS recorded $87 \mathrm{fb}^{-1}$ of data at a center-of-mass energy of 13 TeV between 2015 and 2017. The calorimetry system performed accordingly to its design values and played a crucial role in the ATLAS physics programme. This contribution gives an overview of the detector operation, monitoring and data quality, as well as the achieved performance, including the calibration and stability of the energy scale, noise level, response uniformity and time resolution of the ATLAS calorimetry system. The upgrade projects of the ATLAS calorimeter system are presented. An upgrade of the LAr trigger readout is necessary for Run-3, where luminosities around $\mathcal{L}~\approx~2-3~\times~10^{34}~\mathrm{cm}^{-2} \mathrm{s}^{-1}$ will be achieved, in order to keep a high signal efficiency. The electronics includes the LAr Trigger Digitizer front-end system that digitizes 34,000 channels at 40 MHz with transverse 12-bit precision after bipolar shaping and the back-end LAr Digital Processing system that computes the energy and time of the signals. Results of the system integration tests are presented along with the overall system design. For the high luminosity phase of the LHC (HL-LHC), the luminosity will increase up to $\mathcal{L}~\approx~7.5~\times~10^{34} \mathrm{cm}^{-2} \mathrm{s}^{-1}$ leading to an average pile-up up to 200 interactions per bunch crossing. The electronics of both calorimeters has to be upgraded to cope with longer latencies of up to $35~\mathrm{\mu s}$ needed by the trigger system for such high pile-up levels. For the Tile system, the photomultiplier signals will be digitized and transferred off-detector to the TileCal PreProcessors (TilePPr) for every bunch crossing, requiring a data bandwidth of 40~Tbps to read out the entire detector. The TilePPr will reconstruct, store and send the calorimeter signals to first level of trigger at a rate of 40 MHz. In parallel, the data samples will be stored in pipeline memories until the reception of the first-level trigger acceptance signal. The data of the selected events by the ATLAS central trigger system will be transferred to the ATLAS global Data AcQuisition (DAQ) system for further processing. Test results of the first prototypes will be presented, along with design studies and simulations of the performance of the readout system.