S. Dubé

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

Sterile neutrinos, if they exist, are potential harbingers for physics beyond the Standard Model. They have the capacity to shed light on our flavor sector, grand unification frameworks, dark matter sector and origins of baryon anti-baryon asymmetry. There have been a few seminal studies that have broached the subject of sterile neutrinos with low, electroweak-scale masses (i.e. $\Lambda_{\text{\tiny{QCD}}} \ll m_{N_R} \ll m_{W^\pm}$) and investigated their reach at hadron colliders using lepton jets. These preliminary studies nevertheless assume background-free scenarios after certain selection criteria which are overly optimistic and untenable in realistic situations. These lead to incorrect projections. The unique signal topology and challenging hadronic environment also make this mass-scale regime ripe for a careful investigation. With the above motivations, we attempt to perform the first systematic study of low, electroweak-scale, right-handed neutrinos at hadron colliders, in this unique signal topology. There are currently no active searches at hadron colliders for sterile neutrino states in this mass range, and we frame the study in the context of the $13\,\rm{TeV}$ high-luminosity Large Hadron Collider and the proposed FCC-hh/SppC $100\,\rm{TeV}$ $pp$-collider.

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25μm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50×250μm2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

We describe a method for interpreting trilepton searches at high energy colliders in a model-independent fashion and apply it to the recent searches at the Tevatron. The key step is to recognize that the trilepton signature is comprised of four experimentally very different channels defined by the number of tau-leptons in the trilepton state. Contributions from these multiple channels to the overall experimental sensitivity (cross section times branching ratio) are model-independent and can be parametrized in terms of relevant new particle masses. Given the trileptonic branching ratios of a specific model, these experimentally obtained multichannel sensitivities can be combined to obtain a cross section measurement that can be used to confront the model with data. Our model-independent results are more widely applicable than the current Tevatron trilepton results which are stated exclusively in terms of mSUGRA parameters of supersymmetry. The technique presented here can be expanded beyond trilepton searches to the more general "inverse problem" of experimentally discriminating between competing models that seek to explain new physics discovered in multiple channels.

We examine a modified SU(2) Skyrme model and its predictions. The model is constructed of higher-order terms in derivatives of the pion field in such a way that the chiral-angle equation remains a differential equation of degree 2.

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fV CO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers.

This dissertation describes a search for the associated production of the supersymmetric particles, the chargino and the neutralino, through their R-parity conserving decays to three leptons and missing energy. This search is carried out using the data collected at the CDF experiment at the Tevatron √s = 1.96 TeV p$\bar{p}$ collider at Fermilab. The results are obtained by combining five independent channels with varying signal to background ratio. Overall, a total of 6.4 ± 1.1 background events from standard model processes and 11.4 ± 1.1 signal events for a particular choice of mSUGRA model parameters are expected. The observation of 7 events in data is consistent with the standard model background expectation, and the mSUGRA model is constrained. Limits are set on the cross section of Chargino-Neutralino pair production, and a limit on the mass of the chargino is extracted. A method of obtaining model-independent results is also discussed.

In this paper, an online voting method for elections in India is initially suggested. The suggested model has higher security as the voter’s raised secure password must be validated prior to the recording of the vote in the major database owned by our nation’s Election Commission. The model’s additional feature allows the voter to verify that the right candidate or party received their vote. In this arrangement, a voter has the option to cast a ballot from a place other than the one designated for them or from their favorite site. Vote counting will be made in an automated fashion under the proposed approach, saving a significant amount of period and allowing our nation’s Commission set for Election to declare the results in a much fast succession. Alongside the password-based authentication, we have also utilized the face-based authentication along with the successful implementation of the OpenCV in addition to the password validation. We describe a model for a web voting entity for India in this application using the above said constituents. When contrasted with the conventional voting system, this version of voting systems seems to be considerably much secure and efficient. The delays and frauds occurring during counting of votes can be easily prevented.

We describe a method for interpreting trilepton searches at high energy colliders in a model-independent fashion and apply it to the recent searches at the Tevatron. The key step is to recognize that the trilepton signature is comprised of four experimentally very different channels defined by the number of tau-leptons in the trilepton state. Contributions from these multiple channels to the overall experimental sensitivity (cross section times branching ratio) are model-independent and can be parametrized in terms of relevant new particle masses. Given the trileptonic branching ratios of a specific model, these experimentally obtained multichannel sensitivities can be combined to obtain a cross section measurement that can be used to confront the model with data. Our model-independent results are more widely applicable than the current Tevatron trilepton results which are stated exclusively in terms of mSUGRA parameters of supersymmetry. The technique presented here can be expanded beyond trilepton searches to the more general inverse problem of experimentally discriminating between competing models that seek to explain new physics discovered in multiple channels.

FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC.It is designed in a 130 nm CMOS process and is based on an array of 80 by 336 pixels, each 50×250 μm 2 for an overall size of about 19×20 mm 2 .Each pixel consists of analog and synthesized digital sections.The analog pixel section is designed for low power consumption and compatibility to several sensor candidates.The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides a solution to record hits timewalk-free.A mixture of techniques is used for yield enhancement.The chip periphery contains a control block, a command decoder and global memory, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which allows data transmission up to 160 Mb/s for the IBL.

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

Searches for associated production of chargino‐neutralino in lepton final states at the Tevatron are summarized in this paper. The results from CDF and DO/ are consistent with the standard model and no signs of chargino‐neutralino production are found. Limits are set on the production cross section by both experiments, and charginos with mass less than ∼145 GeV/c2 are excluded in favorable scenarios.

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer.