N. Demaria

The silicon strip microvertex detector of the DELPHI experiment at the CERN LEP collider has been recently upgraded from two coordinates (RΦ only) to three coordinates reconstruction (RΦ and z). The new Microvertex detector consists of 125 952 readout channels, and uses novel techniques to obtain the third coordinate. These include the use of AC coupled double sided silicon detectors with strips orthogonal to each other on opposite sides of the detector wafer. The routing of signals from the z strips to the end of the detector modules is done with a second metal layer on the detector surface, thus keeping the material in the sensitive area to a minimum. Pairs of wafers are daisy chained, with the wafers within each pair flipped with respect to each other in order to minimize the load capacitance on the readout amplifiers. The design of the detector and its various components are described. Results on the performance of the new detector are presented, with special emphasis on alignment, intrinsic precision and impact parameter resolution. The new detector has been taking data since spring of 1994, performing up to design specifications.

The DELPHI Silicon Tracker, an ensemble of microstrips, ministrips and pixels, was completed in 1997 and has accumulated over 70pb−1 of high-energy data. The Tracker is optimised for the LEP2 physics programme. It consists of a silicon microstrip barrel and endcaps with layers of silicon pixel and ministrip detectors. In the barrel part, three-dimensional b tagging information is available down to a polar angle of 25°. Impact parameter resolutions have been measured of 28μm ⊕71/(psin3/2θ)μm in Rφ and 34μm ⊕69/pμm in Rz, where p is the track momentum in GeV/c. The amount of material has been kept low with the use of double-sided detectors, double-metal readout, and light mechanics. The pixels have dimensions of 330×330μm2 and the ministrips have a readout pitch of 200μm. The forward part of the detector shows average efficiencies of more than 96%, has signal-to-noise ratios of up to 40 in the ministrips, and noise levels at the level of less than one part per million in the pixels. Measurements of space points with low backgrounds are provided, leading to a vastly improved tracking efficiency for the region with polar angle less than 25°.

The Compact Muon Solenoid (CMS) is one of the experiments at the Large Hadron Collider (LHC) under construction at CERN. Its inner tracking system consist of the world largest Silicon Strip Tracker (SST). In total it implements 24,244 silicon sensors covering an area of 206m2. To construct a large system of this size and ensure its functionality for the full lifetime of 10 years under LHC condition, the CMS collaboration developed an elaborate design and a detailed quality assurance program. This paper describes the strategy and shows first results on sensor qualification.

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

This work presents a customized 110 nm CMOS process on high-resistivity substrate tailored for the production of fully-depleted pixel sensors. Starting from n-type substrates, customized surface implantations have been introduced to enable fast and efficient collection of the charge generated by ionizing particles or radiation. Double-sided processing has been used to define the backside electrode and the termination structures needed to bias the sensors at high voltage. A first run showing the feasibility of 300 μm-thick fully-depleted sensors was completed, and several test devices designed for the assessment of the process were fabricated together with a 24 × 24 pixels array with 50 μm pitch. The main technological challenges and the customization of the process are discussed, and electrical measurements on test devices demonstrating the functionality of the termination structures, the full depletion of the substrate and the fast charge collection are presented.

We present a monolithic pixel sensor developed in the framework of the LePIX project aimed at tracking/triggering tasks where high granularity, low power consumption, material budget, radiation hardness and production costs are a concern. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This maintains the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, but offers charge collection by drift from a depleted region and therefore an excellent signal to noise ratio and a radiation tolerance superior to conventional undepleted MAPS. Measurement results obtained with the first prototypes from laser, radioactive source and beam test experiments are described. The excellent signal-to-noise performance is demonstrated by the capability of the device to separate the peaks in the spectrum of a 55Fe source. We will also highlight the interaction between pixel cell design and architecture which points toward a very precise direction in the development of such depleted monolithic pixel devices for high energy physics.

A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. The sensor leakage current is compensated by the same feedback network. A track-and-latch voltage comparator is adopted for the hit discrimination. The hit generation is synchronized with a 40 MHz clock, minimizing time-walk issues in the time-stamp assignment. Fast ToT charge encoding up to 8-bit resolution can be retrieved at the pixel level exploiting a high-frequency self-generated clock signal. This is obtained by turning the latch into a voltage-controlled oscillator (VCO) using asynchronous logic. Pixel-to-pixel threshold variations are compensated by means of an autozeroed scheme, thus avoiding the need of a on-pixel D/A converter. An array of 8 × 8 cells with 50 μm × 50 μm pixel size has been prototyped. Design specifications, implementation and test results are discussed.

In the context of the development of radiation hard silicon microstrip detectors for the CMS Tracker, we have investigated the dependence of interstrip and backplane capacitance as well as depletion and breakdown voltage on the design parameters and substrate characteristics of the devices. Measurements have been made for strip pitches between 60 and 240μm and various strip implants and metal widths, using multi-geometry devices, fabricated on wafers of either 〈111〉 or 〈100〉 crystal orientation, of resistivities between 1 and 6kΩcm and of thicknesses between 300 and 410μm. The effect of irradiation on properties of devices has been studied with 24GeV/c protons up to a fluence of 4.3×1014cm−2.

Interstrip and backplane capacitances on silicon microstrip detectors with p+ strip on n substrate of 320μm thickness were measured for pitches between 60 and 240μm and width over pitch ratios between 0.13 and 0.5. Parametrisations of capacitance w.r.t. pitch and width were compared with data. The detectors were measured before and after being irradiated to a fluence of 4×1014protons/cm2 of 24GeV/c momentum. The effect of the crystal orientation of the silicon has been found to have a relevant influence on the surface radiation damage, favouring the choice of a 〈100〉 substrate. Working at high bias (up to 500 V in CMS) might be critical for the stability of detector, for a small width over pitch ratio. The influence of having a metal strip larger than the p+ implant has been studied and found to enhance the stability.

This work describes the design, in 65 nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC . Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to several hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

The LePix project aims at developing monolithic pixel detectors in a 90 nm CMOS technology ported on moderate resistivity substrate. The radiation tolerance of the base material, which is an order of magnitude higher doped than standard high resistivity detectors, and which underwent the full advanced CMOS process, has been investigated. Diodes of about 1 mm2 and pixel matrices were irradiated with neutrons at fluences from 1012 n/cm2 to 2×1015n/cm2 and characterized using CV and IV measurements. Matrices have also been irradiated with Xrays and withstand at least 10 Mrad.

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project.

Due to the large expected instantaneous luminosity, the future HL-LHC upgrade sets strong requirements on the radiation hardness of the CMS detector Inner Tracker. Sensors based on 3D pixel technology, with its superior radiation tolerance, comply with these extreme conditions. A full study and characterization of pixelated 3D sensors fabricated by FBK is presented here. The sensors were bump-bonded to RD53A readout chips and measured at several CERN SPS test beams. Results on charge collection and efficiency, for both non-irradiated and irradiated up to 1016 neq/cm2 samples, are presented. Two main studies are described: in the first the behaviour of the sensor is qualified as a function of irradiation, while kept under identical conditions; in the second the response is measured under typical operating conditions.

This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

A novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed.

The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm 2 ) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades.It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes.The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . ENC value is below 100 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> for an input capacitance of 50 fF and in-time threshold below 1000 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> . Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

The DELPHI Vertex Detector has been upgraded for LEP200 with 2 layers of pixel detectors and 2 layers of ministrips as endcaps, thus covering the polar angular range between 10° and 21° and allowing for standalone pattern recognition. During the 1995/96 shutdown the first 95 modules were installed and the installation was completed in May 97 with all 152 modules. Production yields and failures during the assembly will be presented. The detector operated at a threshold of around 9000 electrons resulting in a number of noisy pixels at the 10−3 level. After masking these hot pixels in the readout, the remaining number of random hits per event is at the 10−6 level. The observed resolution of about 100 μm is close to the expectation for binary readout. The track reconstruction efficiency increased by more than 100% in the central part of the forward tracker.

The subsystems of the CMS silicon strip tracker were integrated and commissioned at the Tracker Integration Facility (TIF) in the period from November 2006 to July 2007. As part of the commissioning, large samples of cosmic ray data were recorded under various running conditions in the absence of a magnetic field. Cosmic rays detected by scintillation counters were used to trigger the readout of up to 15\,\% of the final silicon strip detector, and over 4.7~million events were recorded. This document describes the cosmic track reconstruction and presents results on the performance of track and hit reconstruction as from dedicated analyses.

We present results obtained with full-size wedge silicon microstrip detectors bonded to APV6 (Raymond et al., Proceedings of the 3rd Workshop on Electronics for LHC Experiments, CERN/LHCC/97-60) readout chips. We used two identical modules, each consisting of two crystals bonded together. One module was irradiated with 1.7×1014neutrons/cm2. The detectors have been characterized both in the laboratory and by exposing them to a beam of minimum ionizing particles. The results obtained are a good starting point for the evaluation of the performance of the “ensemble” detector plus readout chip in a version very similar to the final production one. We detected the signal from minimum ionizing particles with a signal-to-noise ratio ranging from 9.3 for the irradiated detector up to 20.5 for the non-irradiated detector, provided the parameters of the readout chips are carefully tuned.

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments.This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications.It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS.The prototype is composed of a matrix of 64×64 pixels with 50 µm × 50 µm cells featuring a compact design, low-noise and low-power performance.The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators.Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e -RMS for 50 fF input capacitance), below 5 µW/pixel power consumption, linear charge measurements up to 30 ke -input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel.A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm 2 hit rate, 1 MHz trigger rate and 12.5 µs trigger latency at HL-LHC.Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration.The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions.All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs.Bias currents and voltages can be monitored by a 12-bit ADC.A bandgap voltage reference circuit provides a stable reference voltage for all these blocks.The readout of triggered data is based on replicated FIFOs placed at the chip periphery.Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer.Triggerless and debug operating modes are also supported.Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions.The digital I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers.All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond.The CHIPIX65 demonstrator was submitted for fabrication on July 2016.It was

Monolithic Active Pixel Sensors are becoming increasingly attractive as charge particle tracking devices for the next generation of High Energy Physics experiments. For this reason several R&D activities are ongoing in different laboratories to improve the performance of conventional monolithics in terms of signal to noise ratio and radiation tolerance. Those improvements come both from the use of different technologies and materials and from the optimization of the front-end electronics. In this context, technologies which allow simultaneous integration of analog and digital electronics in the same pixel are also increasingly exploited. Here, a versatile readout electronics has been specifically developed for a detailed characterization of MAPS with an expected depletion depth of more than 30 μm. Different silicon substrates have been explored to achieve the best performance. The ASIC prototype has been fabricated in 0.11 μm CMOS technology with a die area of 2×2 mm2 and a low voltage operation of 1.2 V. The test chip consists of a matrix of 24×24 pixel units organized in 4 independent sectors and an End of Column logic. The in-pixel electronics fits an area of 30×30 μm2 and it is therefore suitable to develop compact monolithic pixels of 40×40 μm2 or more. The strong point of such readout system is the flexibility which allows to get a low power consumption, a very easy scalability and a good adaptability for both sensor polarities. Hereafter, the front-end electronics is described and detailed tests obtained on a first submission presented.

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC.The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments.Some details on the improvements implemented in the analog front-ends are provided in the paper.

The High Luminosity Large Hadron Collider (HL-LHC) at CERN will constitute a new frontier for the particle physics after the year 2027. Experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sensors and electronics will have a main role in this. This paper describes the recent developments in 65 nm CMOS technology for readout ASIC chips in future High Energy Physics (HEP) experiments. These allow unprecedented performance in terms of speed, noise, power consumption and granularity of the tracking detectors.

The High Luminosity Large Hadron Collider (HL-LHC) will constitute a new frontier for the particle physics after the year 2024. The CERN experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sensors and electronics will be have a main role on this. This paper describes the recent developments in 65nm CMOS technology for readout ASICS of future HEP experiments. These allow unprecedented performance in term of speed, low noise, low power consumption and highly granular tracking detectors.

This paper describes the main achievements in the development of radiation resistant silicon detectors to be used in the CMS tracker. After a general description of the basic requirements for the operation of large semiconductor systems in the LHC environment, the issue of radiation resistance is discussed in detail. Advantages and disadvantages of the different technological options are presented for comparison. Laboratory measurements and test beam data are used to check the performance of several series of prototypes fabricated by different companies. The expected performance of the final detector modules are presented together with preliminary test beam results on system prototypes.

The CMS Silicon Tracker is going to be the largest silicon detector made so far, with about 210 square meters of sensitive area. The CMS Tracker collaboration, after the completion of the R& D phase, has put a lot of effort in finalizing the design of the silicon sensors, electronics hybrid, APV chip and many other crucial components in order to make such a detector possible. Many laboratory tests and test beam studies have been done. The project is now moving toward mass production. In this paper an overview of the CMS Silicon Tracker is made describing many of the progresses made on basics components of the Silicon Tracker.

In 1996 the DELPHI experiment at LEP has upgraded its silicon tracker. In the forward region, pixel detectors were installed. The pixel commissioning and the first results are reported.

This report describes a silicon-tungsten electromagnetic calorimeter used to determine some beam properties and luminosity in the DELPHI experiment at LEP. The polar angular range covered by this detector is 5–8 mrad, which allows the detection of a Bhabha rate about 10 times the rate of produced Z particles at the peak cross section.

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

In recent years Monolithic Active Pixel Sensors are becoming increasingly attractive for High Energy Physics experiments. Several R&D activities are ongoing worldwide to improve the performance of conventional monolithic pixels in terms of speed and radiation tolerance. These improvements come both from the optimization of the substrate material and the design of the front-end electronics. In the framework of an R&D project on CMOS monolithic sensors, a versatile readout electronics has been developed. The purpose is to have a flexible system to test different sensor geometries and substrates, allowing a detailed analog characterization and the study of effects that arise in complex mixed signal chips such as digital induced noise. The ASIC prototype, MATISSE, has been fabricated in 0.11 $\mu$m CMOS technology with a die area of 2$\times$2 mm$^2$ and a low voltage operation of 1.2 V. Hereafter, the front-end electronics are described and the first results from the characterization are reported.

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and large pixel chip size (~2×2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high hit rate (3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 μs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

Data taken by DELPHI during the 1995 and 1996 LEP runs have been used to search for the supersymmetric partners of electron, muon and tau leptons and of top and bottom quarks. The observations are in agreement with standard model predictions. Limits are set on sfermion masses. Searches for long lived scalar leptons from low scale supersymmetry breaking models exclude stau masses below 55 GeV/c2 at the 95% confidence level, irrespective of the gravitino mass.

The CMS experiment at the LHC will comprise a large silicon strip tracker. This article highlights some of the results obtained in the R&D studies for the optimization of its silicon sensors. Measurements of the capacitances and of the high voltage stability of the devices are presented before and after irradiation to the dose expected after the full lifetime of the tracker.

The CMS Silicon tracker consists of 70m2 of microstrip sensors which design will be finalized at the end of 1999 on the basis of systematic studies of device characteristics as function of the most important parameters. A fundamental constraint comes from the fact that the detector has to be operated in a very hostile radiation environment with full efficiency. We present an overview of the current results and prospects for converging on a final set of parameters for the silicon tracker sensors.

For the construction of the silicon microstrip detectors for the Tracker of the CMS experiment, two different substrate choices were investigated: A high-resistivity (6 k cm) substrate with (111) crystalorientation and a low-resistivity (2k cm) one with (100) crystalorientation. The interstrip and backplane capacitances were measured before and after the exposure to radiation in a range of strip pitches from 60 μm to 240 μm and for values of the width-over-pitch ratio between 0.1 and 0.5.

The breakdown performance of CMS barrelmodule prototype detectors and test devices with single and multi-guard structures were studied before and after neutron irradiation up to 2·1014 1 MeV equivalent neutrons. Before irradiation avalanche breakdown occurred at the guard ring implant edges. We measured 100–300 V higher breakdown voltage values for the devices with multi-guard than for devices with single-guard ring. After irradiation and type inversion the breakdown was smoother than before irradiation and the breakdown voltage value increased to 500–600 V for most of the devices.

Results are presented on the radiation and magnetic tests carried out in May and July 2003 on the SASY power supply developed by CAEN for the CMS Silicon Tracker Detector. In particular, using the test equipment developed at Torino INFN laboratory Single Event Upsets both on the analogue and in the digital circuits of the power supply have been detected online. The experimental procedure is described at length and the results are discussed in the perspective of 10 years LHC running.

The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout chips, both in terms of performances and reliability. To face these challenges, the use of a more downscaled CMOS technology compared to previous projects is necessary. The CERN RD53 collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology and to develop tools and frameworks which will help to design future pixel detectors. This paper gives a short overview of the RD53 collaboration activities and describes some examples of recent developments.

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

This paper describes the Silicon microstrip Tracker of the CMS experiment at LHC. It consists of a barrel part with 5 layers and two endcaps with 10 disks each. About 10 000 single-sided equivalent modules have to be built, each one carrying two daisy-chained silicon detectors and their front-end electronics. Back-to-back modules are used to read-out the radial coordinate. The tracker will be operated in an environment kept at a temperature of T=−10°C to minimize the Si sensors radiation damage. Heavily irradiated detectors will be safely operated due to the high-voltage capability of the sensors. Full-size mechanical prototypes have been built to check the system aspects before starting the construction.

An innovative synchronous analog front-end for pixel detectors at HL-LHC has been designed. 600 Mrad TID irradiation at -20°C has been performed. Measurement results are presented and discussed.

The inner portion of the CMS microstrip Tracker consists of 3540 silicon detector modules; its construction has been under full responsibility of seven INFN (Istituto Nazionale di Fisica Nucleare) and University laboratories in Italy. In this note procedures and strategies, which were developed and perfected to qualify the Tracker Inner Barrel and Inner Disks modules for installation, are described. In particular the tests required to select highly reliable detector modules are illustrated and a summary of the results from the full Inner Tracker module test is presented. 1) INFN sez. di Catania and Universita di Catania, Italy 2) INFN sez. di Perugia and Universita di Perugia, Italy 3) INFN sez. di Pisa and Scuola Normale Superiore di Pisa, Italy 4) INFN sez. di Pisa and Universita di Pisa, Italy 5) INFN sez. di Pisa, Italy 6) INFN sez. di Torino and Universita di Torino, Italy 7) INFN sez. di Torino, Italy 8) INFN sez. di Firenze, Italy 9) INFN sez. di Bari and Dipartimento Interateneo di Fisica di Bari, Italy 10) INFN sez. di Bari, Italy 11) INFN sez. di Padova, Italy 12) INFN sez. di Firenze and Universita di Firenze, Italy 13) INFN sez. di Padova and Universita di Padova, Italy 14) INFN sez. di Perugia, Italy a) On leave from ISS, Bucharest, Romania b) On leave from IFIN-HH, Bucharest, Romania c) Corresponding Author

The CMS Inner Tracker, in the High Luminosity LHC (HL-LHC) phase, will be instrumented with approximately 13 × 103 CMS Readout Chips (CROCs). This integrated circuit has been developed by the RD53 Collaboration in order to work reliably in the high hit rates and radiation doses of HL-LHC. The CMS Readout Chip includes a novel powering scheme, a very complex digital circuitry, and a low power analogue front-end. The first batch of prototype CROC wafers has been received in the third quarter of 2021 and several wafers have been tested in 2022 with the wafer-level testing (WLT) setup developed at INFN Torino. The WLT data are being used to produce prototype detector modules, to characterise the CROC v1 before the submission of the final version of the chip, and to estimate wafer yields. This paper describes the wafer-level testing apparatus and the major results obtained in the first waferprobing campaign.

We report selected results of laboratory measurements and beam tests of heavily irradiated microstrip silicon detectors. The detectors were single-sided devices, produced by different manufacturers and irradiated with different sources, for several total ionizing doses and fluences up to 4 /spl times/10/sup 14/ 1-MeV-equivalent neutrons per cm/sup 2/. Strip resistance and capacitance, detector leakage currents and breakdown performance were measured before and after irradiations. Signal-to-noise ratio and detector efficiency were studied in beam tests, for different values of the detector temperature and of the read-out pitch, as a function of the detector bias voltage. The goal of these test is to optimise the design of the final prototypes for the Silicon Strip Tracker of the CMS experiment at the CERN LHC collider.

The CMS silicon strip tracker involves about 70 m2 of instrumented silicon, with approximately 18500 microstrip detectors read out by 5 × 106 electronics channels. It has to satisfy a set of stringent requirements imposed by the environment and by the physics expected at the LHC: low cell occupancy and good resolution, radiation hardness aided by adequate cooling, low mass combined with high stability. These conditions have been incorporated in a highly modular design of the detector modules and their support structures, chosen to facilitate construction and to allow for easy assembly and maintenance.

The Delphi Collaboration has measured the lifetime of b-hadrons using several different methods. In this talk those exploited only by Delphi and that employ original ideas are presented: for the b-baryons lifetime the p-μ correlation; for the Bs0 the -μ, Ds-h correlations and Ds inclusive analysis. The measurement of the average lifetime of b- hadrons using the impact parameters and the vertices of hadronic final states is also presented.