Luca Pacher

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

We present the experimental results obtained with TOFPET2, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit is designed in CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration ADCs in each channel. The chip tape-out was done in September 2016 and first tests started in beginning March 2017. Coincidence Time Resolution (CTR) of 164ps FWHM has been measured with 22Na point source. The energy resolution achieved for the 511keV peak is 10.5% FWHM.

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. The sensor leakage current is compensated by the same feedback network. A track-and-latch voltage comparator is adopted for the hit discrimination. The hit generation is synchronized with a 40 MHz clock, minimizing time-walk issues in the time-stamp assignment. Fast ToT charge encoding up to 8-bit resolution can be retrieved at the pixel level exploiting a high-frequency self-generated clock signal. This is obtained by turning the latch into a voltage-controlled oscillator (VCO) using asynchronous logic. Pixel-to-pixel threshold variations are compensated by means of an autozeroed scheme, thus avoiding the need of a on-pixel D/A converter. An array of 8 × 8 cells with 50 μm × 50 μm pixel size has been prototyped. Design specifications, implementation and test results are discussed.

This work describes the design, in 65 nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC . Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to several hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

The LePix project aims at developing monolithic pixel detectors in a 90 nm CMOS technology ported on moderate resistivity substrate. The radiation tolerance of the base material, which is an order of magnitude higher doped than standard high resistivity detectors, and which underwent the full advanced CMOS process, has been investigated. Diodes of about 1 mm2 and pixel matrices were irradiated with neutrons at fluences from 1012 n/cm2 to 2×1015n/cm2 and characterized using CV and IV measurements. Matrices have also been irradiated with Xrays and withstand at least 10 Mrad.

This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

A novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed.

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm 2 ) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades.It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes.The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . ENC value is below 100 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> for an input capacitance of 50 fF and in-time threshold below 1000 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> . Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments.This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications.It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS.The prototype is composed of a matrix of 64×64 pixels with 50 µm × 50 µm cells featuring a compact design, low-noise and low-power performance.The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators.Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e -RMS for 50 fF input capacitance), below 5 µW/pixel power consumption, linear charge measurements up to 30 ke -input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel.A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm 2 hit rate, 1 MHz trigger rate and 12.5 µs trigger latency at HL-LHC.Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration.The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions.All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs.Bias currents and voltages can be monitored by a 12-bit ADC.A bandgap voltage reference circuit provides a stable reference voltage for all these blocks.The readout of triggered data is based on replicated FIFOs placed at the chip periphery.Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer.Triggerless and debug operating modes are also supported.Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions.The digital I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers.All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond.The CHIPIX65 demonstrator was submitted for fabrication on July 2016.It was

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC.The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments.Some details on the improvements implemented in the analog front-ends are provided in the paper.

The investigation of secondary effects induced by ionizing radiation represents a new and ever-growing research field in radiobiology. This new paradigm cannot be investigated only using standard instrumentation and methodologies, but rather requires novel technologies to achieve significant progress. In this framework, we developed diamond-based sensors that allow simultaneous real-time measurements with a high spatial resolution of the secretory activity of a network of cells cultured on the device, as well as of the dose at which they are exposed during irradiation experiments. The devices were functionally characterized by testing both the above-mentioned detection schemes, namely: amperometric measurements of neurotransmitter release from excitable cells (such as dopamine or adrenaline) and dosimetric evaluation using different ionizing particles (alpha particle and X-ray photons). Finally, the sensors were employed to investigate the effects induced by X-rays on the exocytotic activity of PC12 neuroendocrine cells by monitoring the modulation of the dopamine release in real-time.

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and large pixel chip size (~2×2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high hit rate (3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 μs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout chips, both in terms of performances and reliability. To face these challenges, the use of a more downscaled CMOS technology compared to previous projects is necessary. The CERN RD53 collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology and to develop tools and frameworks which will help to design future pixel detectors. This paper gives a short overview of the RD53 collaboration activities and describes some examples of recent developments.

An innovative synchronous analog front-end for pixel detectors at HL-LHC has been designed. 600 Mrad TID irradiation at -20°C has been performed. Measurement results are presented and discussed.

In the framework of the CHIPIX65 project, that aims at prototyping a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC, a 12-bit ADC has been designed for monitoring slowly varying signals and dc voltage reference levels. The architecture of the ADC is based on a dualslope integrating structure and the circuit has a 460umx275um area. All the analog blocks have been placed in a deep n-well for better rejecting noise coming from the digital part. In addition, an innovative self-calibration procedure has been implemented in hardware to set the internal configuration registers of the ADC, which control its configurable parameters, as soon as the circuit is powered up. Two versions of the ADC have been prototyped and the second one has been also integrated in the CHIPIX65 demonstrator ASIC. First measurement tests have been carried out to validate the performance of the circuit in terms of linearity and resolution.