L. Calligaris

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2–3 GeV within 4 μs so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to an average of 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.

Abstract We present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine card for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN and we show the addition of new features and support for new protocols in the firmware of the controller mezzanine card.

Abstract This work presents the development of an Intelligent Platform Management Controller mezzanine in a Mini DIMM form factor for use in electronic boards compliant to the PICMG Advanced Telecommunication Computing Architecture (ATCA) standard. The module is based on an STMicroelectronics STM32H745 microcontroller running the OpenIPMC open-source software. The mezzanine has been successfully tested on a variety of ATCA boards being proposed for the upgrade of the experiments at the HL-LHC, with its design and firmware being distributed under open-source hardware license.

CUORE will be an array of 988 TeO2 bolometers (5 × 5 × 5 cm3) held at about 10 mK. It will study the very rare double β decay process from 130Te. The electrical connections of the array to the room temperature electronics will consist in about 2000 wires. We will describe the design and characterization of the 3 interconnection sectors going from the detectors to the mixing chamber, the coldest stage at which the array is thermally and mechanically anchored, and from the mixing chamber to room temperature. The lower part consists of a set of 2.3 m long, 50 μm thick, Cu-insulator tapes having PEN (Polyethylene 2.6 Naphthalate) substrate, on which a pattern of copper tracks are etched. The differential layout pattern chosen allows obtaining a signal cross talk between adjacent channels of about 0.024%, together with a capacitance of about 26 pF/m and a resistance larger than 200 GΩ/m. On the top of the mixing chamber, Cu-Kapton boards are used to join the tapes to the second upward-going 2 m long links, implemented with twisted NbTi wires, interwoven in a NOMEX® texture. NbTi-NOMEX link features about 100 pF/m and negligible level of cross-talk. The radioactivity content of Cu-PEN tapes, Cu-Kapton boards, NbTi-NOMEX ribbons and connectors has been investigated and found to be compliant with the experimental requirements. A mechanical study has been done to quote the vibration transmission properties of the highly packaged tapes.

OpenIPMC is a free and open source firmware designed to operate as an Intelligent Platform Management Controller (IPMC). An IPMC is a fundamental component of electronic boards conformant to the Advanced Telecommunications Computing Architecture (ATCA) standard, currently being adopted by a number of high energy physics experiments, and is responsible for monitoring the health parameters of the board, managing its power states, and providing board control, debug and recovery functions to remote clients. OpenIPMC is based on the FreeRTOS real-time operating system and is designed to be architecture-independent, allowing it to be built for a variety of different Microcontrollers. Having a fully free and open source code is an innovative aspect for this kind of firmware, allowing full customization by the user. In this work we present the features and structure of OpenIPMC and its example implementations on Xilinx Zynq UltraScale+ (ZynqUS+), Espressif ESP32, and ST Microelectronics STM32 architectures.

A new tracking system is under development for operation in the CMS experiment at the High Luminosity LHC. It includes an outer tracker which will construct stubs, built by correlating clusters in two closely spaced sensor layers for the rejection of hits from low transverse momentum tracks, and transmit them off-detector at 40 MHz. If tracker data is to contribute to keeping the Level-1 trigger rate at around 750 kHz under increased luminosity, a crucial component of the upgrade will be the ability to identify tracks with transverse momentum above 3 GeV/c by building tracks out of stubs. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are identified using a projective binning algorithm based on the Hough Transform. A hardware system based on the MP7 MicroTCA processing card has been assembled, demonstrating a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This paper outlines the system architecture and algorithms employed, highlighting some of the first results from the hardware demonstrator and discusses the prospects and performance of the completed track finder.

Data acquisition systems (DAQ) for high energy physics experiments utilize complex FPGAs to handle unprecedented high data rates, especially in the first stages of the data processing chain. The complexity of developing and commissioning these systems increases as additional local processing intelligence is placed closer to the detector directly on the ATCA blades. On the other hand, sophisticated slow control is as well desired. In this contribution, we introduce a novel solution for ATCA based systems, which combines the IPMI, a Linux based slow-control software, and an FPGA for custom slow-control tasks in one single Zynq Ultrascale+ (ZUS+) System-on-Chip (SoC) module.

The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider.Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module.Accepted stubs are transmitted off-detector for further processing at 40 MHz.In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process.For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us.Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach.As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder.The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.

Abstract The Phase-2 Upgrade of the CMS experiment is designed to prepare its detectors for operations at the High Luminosity Large Hadron Collider (HL-LHC). The upgraded collider, scheduled to start operations in 2027, will lead to challenging conditions in terms of data throughput, pile-up and radiation. For these reasons the tracker detector will be entirely replaced by a new detector, the Phase-2 tracker. We present the status of the design, test and validation of the components of the Phase-2 tracker, and its read-out, calibration, control, and data processing chains.

Abstract The Large Hadron Collider (LHC) at CERN will undergo major upgrades to increase the instantaneous luminosity up to 5–7.5×10 34 cm -2 s -1 . This High Luminosity upgrade of the LHC (HL-LHC) will deliver a total of 3000–4000 fb -1 of proton-proton collisions at a center-of-mass energy of 13–14 TeV. To cope with these challenging environmental conditions, the strip tracker of the CMS experiment will be upgraded using modules with two closely-spaced silicon sensors to provide information to include tracking in the Level-1 trigger selection. This paper describes the performance, in a test beam experiment, of the first prototype module based on the final version of the CMS Binary Chip front-end ASIC before and after the module was irradiated with neutrons. Results demonstrate that the prototype module satisfies the requirements, providing efficient tracking information, after being irradiated with a total fluence comparable to the one expected through the lifetime of the experiment.

We present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine card for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN and we show the addition of new features and support for new protocols in the firmware of the controller mezzanine card.

The CMS collaboration is preparing a major upgrade of its detector, so it can operate during the high luminosity run of the LHC from 2026. The upgraded tracker electronics will reconstruct the trajectories of charged particles within a latency of a few microseconds, so that they can be used by the level-1 trigger. An emulation framework, CIDAF, has been developed to provide a reference for a proposed FPGA-based implementation of this track finder, which employs a Time-Multiplexed (TM) technique for data processing.

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC).A crucial component of this upgrade will be the ability to reconstruct within a few microseconds all charged particle tracks with transverse momentum above 3 GeV, so they can be used in the Level-1 trigger decision.A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform followed by a track fitting based on the linear regression technique.A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters.It successfully operates on one eighth of the tracker solid angle at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying latency constraints.The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.