K. Androsov

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm 2 ) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades.It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes.The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC.The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments.Some details on the improvements implemented in the analog front-ends are provided in the paper.

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and large pixel chip size (~2×2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high hit rate (3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 μs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

Next generation of pixel detectors for the first layers of the ATLAS and CMS experiments at the High-Luminosity Large Hadron Collider (HL-LHC) are expected to sustain the particle flow rates up to ~2 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The very high radiation levels and small available space makes it impossible to envisage optical conversion on chip, which should be done using electrical links, implying that a significant material contribution will be associated with data transport out of the detector volume. In this paper the results of the implementation of a lossless arithmetic data compression are presented. The proposed implementation achieves an average bandwidth reduction factor between 1.7 and 2.2, depending on the readout configuration. In addition, it is shown that the similar compression ratio can be achieved by using Huffman coding.

The first search for a heavy charged vector boson in the final state with a tau lepton and a neutrino is reported, using 19.7 fb−1 of LHC data at s=8TeV. A signal would appear as an excess of events with high transverse mass, where the standard model background is low. No excess is observed. Limits are set on a model in which the W′ decays preferentially to fermions of the third generation. These results substantially extend previous constraints on this model. Masses below 2.0 to 2.7 TeV are excluded, depending on the model parameters. In addition, the existence of a W′ boson with universal fermion couplings is excluded at 95% confidence level, for W′ masses below 2.7 TeV. For further reinterpretation a model-independent limit on potential signals for various transverse mass thresholds is also presented.

The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout chips, both in terms of performances and reliability. To face these challenges, the use of a more downscaled CMOS technology compared to previous projects is necessary. The CERN RD53 collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology and to develop tools and frameworks which will help to design future pixel detectors. This paper gives a short overview of the RD53 collaboration activities and describes some examples of recent developments.

A search for a heavy scalar Higgs boson H decaying into a pair of lighter (Standard Model like) 125 GeV Higgs bosons h or a pseudo scalar Higgs boson A decaying into a Z boson and an h boson is presented [1].This search is performed on data collected by CMS experiment during 2012 proton-proton collisions, corresponding to an integrated luminosity of 19.7 fb -1 .A final state consisting of two τ leptons and two b-jets is searched for the H → hh decay and a final state consisting of two τ leptons and two additional leptons, compatible with being the decay products of a Z boson, is searched for the decay A → Zh.This search is interpreted in the contexts of both the minimal supersymmetric extension to the standard model and two Higgs Doublet Models.No excess is found and upper limits at 95% confidence level are set on the production cross-section times branching ratio in the mass range 220 < m A < 350 GeV and 260 < m H < 350 GeV.

The Silicon strip sensors in high energy physics collider experiments have excellent capabilities of vertexing and tracking of incoming particles produced as a result of collision. These sensors are placed in intense radiation environment and hence undergo severe bulk and surface radiation damage. In order to operate these detectors with good physics performance, they must be subjected to stringent tolerance limits for their design parameters. These design parameters include global, strip and inter-strip parameters. The sensors are characterized for these parameters in temperature and humidity controlled environment, which are then accepted or rejected based on the constraints imposed on these parameters offered by a specific experiment.Our group at the University of Delhi is engaged in the process of developing a silicon sensor quality control centre for testing a large number of silicon micro-strip sensors. The primary objective of this facility is the qualification of these sensors for the outer tracker of the CMS experiment in High-Luminosity LHC upgrade. The system consists of a probe station and a set of electrical characterization units. The entire system is interfaced through the Automated Characterization Suite (ACS) software which allows the automatic characterization of the whole multistrip sensor without any manual intervention. The set-up has been under testing for measurements involving global, strip and inter-strip parameters. In this work, we present the details of this characterization system and measurements performed on some silicon strip sensors. To calibrate our setup the same set of measurements are performed with the setup available at the University of Pisa, Italy. The measurements performed using these two setups are found to be consistent with each other.

Silicon detectors are expected to experience an unprecedented radiation flux in the future upgrades of the detectors at the Large Hadron Collider (LHC). The challenging radiation environment of these experiments will severely affect the performance of such detectors, degrading their detection capabilities and imposing severe operational conditions. The modeling of the detectors through Monte Carlo simulation represents a necessary step for the detailed understanding of the silicon detector performance before and after radiation damage; also for setting up optimized design rules aiming to mitigate the detrimental effect of the radiation damage. In the present work, a comparison of simulation results, obtained from- Technology Computer-Aided Design (TCAD) simulation software: Silvaco and Synopsys- used to predict silicon detectors performance, is presented. The effects of radiation damage are incorporated in the TCADs, using an effective multiple traps model. A systematic study of the sensitivity of the silicon detector's macroscopic parameters to the modeling of traps is performed. The simulation results for static electrical parameters, such as the leakage current and the full depletion voltage, obtained by the TCADs are presented and compared.