G. Iles

The FC7 is a flexible, μTCA compatible Advanced Mezzanine Card (AMC) for generic data acquisition/control applications. Built around the Xilinx Kintex-7 FPGA, the FC7 provides developers with a platform which has access to a large array of configurable I/O, primarily delivered from on-board FPGA Mezzanine Card (FMC) sockets. Targeting users of high-speed optical links in high energy physics experiments, the board is capable of driving and receiving links up to 10 Gbps. This paper presents test results from the first set of pre-production prototypes and reports on FC7 uses and applications towards upgrades in CMS.

Test results are presented for two AMC cards, the ``CTP6'' and ``MP7''. The two cards take different approaches to connectivity: the CTP-6 has fully-populated backplane connectivity and a 396 Gbps asymmetric, optical interface, whilst the MP7 instead favours a 1.4 Tbps, symmetric, all-optical interface. The challenges of designing the MP7 card necessitated the development of several test cards; the results of which are presented.

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2–3 GeV within 4 μs so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to an average of 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.

Serenity is an ATCA prototyping platform designed to explore alternative, novel design choices for CMS Phase-2.It uses a newly available interconnect technology from Samtec (Z-RAY) to mount a removable processing unit (FPGA) that should mitigate risk and provides significant flexibility in processing unit choice and connectivity.We explore the pros and cons of using an industry-standard Computer-On-Module running standard Centos Linux and a small service FPGA for low level control.Specially designed Kapton heaters have been used to validate the thermal design of the card and broader considerations of ATCA systems.

Abstract The Serenity-S1 is a production-optimised Advanced Telecommunications Computing Architecture (ATCA) processing blade based on the AMD Xilinx Virtex Ultrascale+ device. It incorporates many developments from the Serenity-A and Serenity-Z prototype cards and, where possible, adopts solutions being used across CERN. Due to the shortage of components during the recent semiconductor crisis, commonly used components in the prototypes had to be replaced by new ones after qualification. In this work, we discuss various improvements to simplify manufacturing, the performance of new components, some of the more difficult aspects of procurement, the performance of production-grade Samtec 25 Gb/s optical firefly parts, and concerns regarding the rack cooling infrastructure.

The MP7 processor card is an all-optical signal processor based on mid-range Xilinx Virtex-7 FPGAs (XC7VX485T or XC7VX690T) in a 1927-pin package. The current version of the card uses the large serial bandwidth of these FPGAs to provide a 0.75+0.75Tbps bidirectional interface, although changes are currently being implemented to push the bandwidth to 0.94+0.94Tbps. The MP7 card was designed before Virtex-7 Engineering Silicon was available and so a lot of design work relied on preliminary documentation and discussion with Xilinx engineers. The MP7 card was, therefore, the first card in the CMS experiment to use Xilinx 7-series FPGAs. The experience of designing for and powering the Virtex-7 are discussed, along with lessons learned. The challenges associated with cooling an FPGA dissipating of-the-order 40W is also discussed.

The Compact Muon Solenoid (CMS) experiment has implemented a sophisticated two-level online selection system that achieves a rejection factor of nearly 105. During Run II, the LHC will increase its centre-of-mass energy up to 13 TeV and progressively reach an instantaneous luminosity of 2 × 1034 cm−2 s−1. In order to guarantee a successful and ambitious physics programme under this intense environment, the CMS Trigger and Data acquisition (DAQ) system has been upgraded. A novel concept for the L1 calorimeter trigger is introduced: the Time Multiplexed Trigger (TMT) . In this design, nine main processors receive each all of the calorimeter data from an entire event provided by 18 preprocessors. This design is not different from that of the CMS DAQ and HLT systems. The advantage of the TMT architecture is that a global view and full granularity of the calorimeters can be exploited by sophisticated algorithms. The goal is to maintain the current thresholds for calorimeter objects and improve the performance for their selection. The performance of these algorithms will be demonstrated, both in terms of efficiency and rate reduction. The callenging aspects of the pile-up mitigation and firmware design will be presented.

When the LHC resumes operation in 2015, the higher centre-of-mass energy and high-luminosity conditions will require significantly more sophisticated algorithms to select interesting physics events within the readout bandwidth limitations. The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps. The upgrade will improve the energy and position resolution of physics objects, enable much improved isolation criteria to be applied to electron and tau objects and facilitate pile-up subtraction to mitigate the effect of the increased number of interactions occurring in each bunch crossing. The design of the upgraded system is summarised with particular emphasis placed on the results of prototype testing and the experience gained which is of general application to the design of such systems.

A new tracking system is under development for operation in the CMS experiment at the High Luminosity LHC. It includes an outer tracker which will construct stubs, built by correlating clusters in two closely spaced sensor layers for the rejection of hits from low transverse momentum tracks, and transmit them off-detector at 40 MHz. If tracker data is to contribute to keeping the Level-1 trigger rate at around 750 kHz under increased luminosity, a crucial component of the upgrade will be the ability to identify tracks with transverse momentum above 3 GeV/c by building tracks out of stubs. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are identified using a projective binning algorithm based on the Hough Transform. A hardware system based on the MP7 MicroTCA processing card has been assembled, demonstrating a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This paper outlines the system architecture and algorithms employed, highlighting some of the first results from the hardware demonstrator and discusses the prospects and performance of the completed track finder.

Abstract In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family Advanced Telecommunications Computing Architecture (ATCA) blades. This paper presents the developments of the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software in the real-time capable processors of the MPSoC. In coordination with the Shelf Manager, once full-power is enabled, a CentOS-based Linux distribution is executed in the application processors of the MPSoC, on which EMPButler and the Serenity Management Shell (SMASH) are running.

The front end driver (FED), is a 9U 400 mm VME64x card designed for reading out the compact muon solenoid (CMS), silicon tracker signals transmitted by the APV25 analogue pipeline application specific integrated circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board field programmable gate arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed

Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was performed in two stages, with the first running in 2015 for proton and heavy ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb−1 of data since the start of the Run II of the Large Hadron Collider (LHC). The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the μTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger processors can be expanded according to the physics needs of CMS. Sophisticated and innovative algorithms are now the core of the first decision layer of the experiment. The system has been able to adapt to the outstanding performance of the LHC, which ran with an instantaneous luminosity well above design. The performance of the system for single physics objects are presented along with the optimizations foreseen to maintain the thresholds for the harsher conditions expected during the LHC Run II and Run III periods.

We have designed and built prototype modules of a large area photon counting hybrid pixel detector. The detector consists of modules each with seven Aladin readout chips solder bump bonded to a silicon pixel detector. Each Aladin chip has 64×64 pixels together with logic to readout the whole array in 400 μs. It is intended to tile an area of 2000×2000 pixels, each of 150 μm×150 μm and capable of up to 1 MHz count rate per pixel. This paper describes the design and operation of the detector and the performance of the existing modules. The measurements demonstrate that the detector can image 19 keV photons at 200 kHz photons per pixel with 3 keV FWHM noise. The detector is intended for X-ray diffraction studies with data capture speeds up to 1000 images per second, independent of the image size.

A small laboratory prototype has been designed for the Compton imaging of annihilation photons produced from positron emitters. Considerations on the design of the scatter collimator are presented and the system configuration is described. The system features a stack of four AC coupled, double-sided silicon strip detectors (6/spl times/6 cm/sup 2/ area, 500 /spl mu/m thickness, 470 /spl mu/m strip pitch, 128 channels/side) in a double Compton configuration and externally triggered readout mode. Signal readout is obtained by bonding two 128-channel low-noise APV6 chips to each detector. Custom electronics have been developed for the chip readout. The system is currently being assembled. The estimated angular resolution of the camera is approximately 4 degrees. High sensitivity could be achieved by extending the number of stack elements and by improving the design of the trigger detector, which presently consists of a small area germanium crystal.

A prototype X-ray detector for energy-dispersive EXAFS has been developed and tested to demonstrate the principle of using silicon microstrip detector technology for this application. Testing took place at the UK Synchrotron Radiation Source, where the absorption spectra of a 5 microm Ni foil and a 25 mM NiCl(2) solution were obtained.

An alternative design for the CMS Global Calorimeter Trigger (GCT) is being implemented. The new design adheres to all the CMS specifications regarding interfaces and functional requirements of the trigger systems. The design is modular, compact, and utilizes proven components. Functionality has been partitioned to allow commissioning in stages corresponding to the different capabilities being made operational. The functional breakdown and hardware platform is presented and discussed. A related paper discusses the firmware required to implement the GCT functionality.

The Front End Driver (FED) is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker signals transmitted by the APV25 analogue pipeline ASICs. The signals are transmitted to each FED via 96 optical fibers at a total input rate corresponding to 3 Gbytes/s. The FED digitizes the signals and processes the data digitally by applying algorithms for pedestal and common mode noise subtraction. The input data rate is reduced using algorithms that search for clusters of hits. Only the cluster data along with trigger information of the event are transmitted to the CMS DAQ system using the SLINK-64 protocol at a maximum rate of 640 Mbytes/s. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays (FPGA). Two FED cards have been manufactured during the last quarter of 2002. Results on the performance of the FED are presented and discussed.

We have developed a 1.5 D CMOS active pixel sensor to be used in conjunction with a scintillator for X-ray imaging. Within the Intelligent Imaging Sensors (I-ImaS) project, multiple sensors will be aligned to form a line-scanning system and its performance evaluated with respect to existing sensors in other digital radiography systems. Each sensor contains a 512×32 array of pixels and the electronics to convert the collected amount of charge to a digital output value. These include programmable gain amplifiers (PGAs) and analogue-to-digital converters (ADCs). The gain of the PGA can be switched between one or two, to increase the sensitivity for smaller collected charge; the ADC is a 14-bit successive approximation with a sampling rate of 1.25 MHz. The ASIC includes a programmable column fixed pattern noise mitigation circuit and a digitally controllable pixel reset mode block. Here we will describe the sensor design and the expected performance.

We have built a back-illuminated, silicon x-ray pixel detector which is bump bonded to an array of readout electronics. The system is intended for x-ray spectroscopy measurement in the 1 keV-25keV range with a resolution of 250eV FWHM. The readout electronics consists of an array of 16 by 16 preamplifiers on the bump bonded integrated circuit, this unit is wire bonded to two 128 channel integrated circuits which have signal shaping, peak-hold and sparcification logic. This paper describes the construction of the silicon detector, the readout electronics and the performance of these components. The energy range of the detector system can be increased by using a GaAs or CdZnTe detector instead of the 300 micrometers -500 micrometers thick silicon pixel detector described here.

The CMS Global Calorimeter Trigger (GCT) has been designed, manufactured and commissioned on a short time schedule of approximately two years. The GCT system has gone through extensive testing on the bench and in-situ and its performance is well understood. This paper describes problems encountered during the project, the solutions to them and possible lessons for future designs, particularly for high speed serial links. The input links have been upgraded from 1.6Gb/s synchronous links to 2.0Gb/s asynchronous links. The existing output links to the Global Trigger (GT) are being replaced. The design for a low latency, high speed serial interface between the GCT and GT, based upon a Xilinx Virtex 5 FPGA is presented.

We have built a back-illuminated, silicon X-ray detector with 16×16 pixels. This is bump-bonded to an integrated circuit containing a corresponding array of pre-amplifiers. The bump-bonded unit is wire bonded to two 128 channel integrated circuits which have signal shaping, peak-hold and sparcification logic. These integrated circuits output the analogue value of the individual X-ray and the address of the 300 μm×300 μm pixel. The system has previously demonstrated X-ray spectroscopy measurement in the 5–40 keV range with a resolution of 1 keV FWHM. This paper describes the performance of the system used in an X-ray diffraction experiment performed on the Daresbury Synchrotron Radiation Source. The second part demonstrates the successful operation of this pixellated detector for spectroscopy. In this part, the variation among the pixel outputs is accounted for without significantly affecting the noise performance.

The Global Calorimeter Trigger (GCT) is a device which uses data from the CMS calorimeters to search for jets, produce isolated and non-isolated electron lists and compute all the transverse and missing transverse energy sums used for the Level-1 trigger decision (L1A). GCT performs these functions by receiving and processing the data from the Regional Calorimeter Trigger (RCT) and transmitting a summary to the Global Trigger (GT) which computes the L1A decision. The GCT must also transmit a copy of the RCT and GCT data to the CMS DAQ. The vast amount of data received by the GCT (230 Gb/s) as well as the necessity for data sharing required by the jet finder impose severe constrains on the GCT design. This paper presents an overview of the revised design, in particular, the algorithms, data flow and associated latency within the revised GCT.

The CMS Global Calorimeter Trigger system performs a wide-variety of calorimeter data processing functions required by the CMS Level-1 trigger.It is responsible for finding and classifying jets and tau-jets, calculating total and missing transverse energy, total transverse energy identified within jets, sorting e/γ candidates, and calculating several quantities based on forward calorimetry for minimumbias triggers.The system is based on high-speed serial optical links and large FPGAs.The system has provided CMS with calorimeter triggers during commissioning and cosmic runs throughout 2008.The performance of the system in validation tests and cosmic runs is presented here.

The Compact Muon Solenoid (CMS) employs a sophisticated two-level online triggering system that has a rejection factor of up to 105. Since the beginning of Run II of LHC, the conditions that CMS operates in have become increasingly challenging. The centre-of-mass energy is now 13 TeV and the instantaneous luminosity currently peaks at 1.5 ×1034 cm−2s−1. In order to keep low physics thresholds and to trigger efficiently in such conditions, the CMS trigger system has been upgraded. A new trigger architecture, the Time Multiplexed Trigger (TMT) has been introduced which allows the full granularity of the calorimeters to be exploited at the first level of the online trigger. The new trigger has also benefited immensely from technological improvements in hardware. Sophisticated algorithms, developed to fully exploit the advantages provided by the new hardware architecture, have been implemented. The new trigger system started taking physics data in 2016 following a commissioning period in 2015, and since then has performed extremely well. The hardware and firmware developments, electron and photon algorithms together with their performance in challenging 2016 conditions is presented.

The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider.Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module.Accepted stubs are transmitted off-detector for further processing at 40 MHz.In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process.For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us.Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach.As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder.The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.

At the HL-LHC, proton bunches will cross each other every 25 ns, producing an average of 140 pp-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5 μs. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.

Collimation of gamma-rays based on Compton scatter could provide in principle high resolution and high sensitivity, thus becoming an advantageous method for the imaging of radioisotopes of clinical interest. A small laboratory prototype of a Compton camera is being constructed in order to initiate studies aimed at assessing the feasibility of Compton imaging of positron emitters. The design of the camera is based on the use of a silicon collimator consisting of a stack of double-sided, AC-coupled microstrip detectors (area 6 x 6 cm(2), 500 pin thickness, 128 channels/side). Two APV6 chips are employed for signal readout on opposite planes of each detector. This work presents the first results on the noise performance of the silicon strip detectors. Measurements of the electrical characteristics of the detector are also reported. On the basis of the measured noise. an angular resolution of approximately 5degrees is predicted for the Compton collimator. (C) 2002 Elsevier Science B.V. All rights reserved.

A large-area pixellated photon counting imaging system, primarily for synchrotron radiation research, is under development. An area of 300 mm×300 mm will be covered by tiling many modules. A module will comprise a 64×448 array of 150 μm×150 μm silicon pixels covering an area of 9.6 nm×67.2 mm. This will be flip chip bonded to 7 ALADIN readout chips, that each contain a 64×64 array of 144 mm×150 μm pixels. Each readout pixel comprises a pre-amplifier, shaper, discriminator, 15-bit counter and 5-bit register that enables threshold adjust, pixel masking and calibrate control. Each pixel is designed to operate at ∼1 MHz providing a count rate capability of ∼109 cm−2 s−1. The system will operate in the energy range from 4 to 25 keV and at a frame rate of up to 1 kHz. The current status of the project is reported, along with the detector guard structure chosen to minimise the dead region around the active volume of the silicon detector.

A digital circuit board, employing Field Programmable Gate Array (FPGA) technology, has been built to emulate the logic of the pipeline memory of the APV25 readout circuit for the CMS Silicon Strip Tracker. The primary function of the APVE design is to prevent buffer overflows in the APV25. It will also provide information to the Front End Drivers (FEDs) to ensure synchronisation throughout the Silicon Strip Tracker. The purpose and functionality of the APVE is presented along with a prediction of the performance from simulation results.

The CMS Global Calorimeter Trigger system's HCAL Muon and Quiet bit reformatting function is being implemented with a novel processing architecture. This architecture utilizes micro TCA, a modern modular communications standard based on high speed serial links, to implement a processing matrix. This matrix is configurable in both logical functionality and data flow, allowing far greater flexibility than current trigger processing systems. In addition, the modular nature of this architecture allows flexibility in scale unmatched by traditional approaches. The Muon and Quiet bit system consists of two major components, a custom micro TCA backplane and processing module. These components are based on Xilinx Virtex5 and Mindspeed crosspoint switch devices, bringing together state of the art FPGA based processing and Telcom switching technologies.

The CMS Global Calorimeter Trigger (GCT) is the device within the Level-1 CMS calorimeter trigger system which is assigned the tasks of finding and sorting forward, central and tau-jet candidates, sorting isolated and non-isolated electron candidates and reading out all of the calorimeter trigger data. The GCT system has been installed and commissioned in the CMS underground cavern. A sophisticated software package has been developed for controlling and configuring the GCT hardware and monitoring the GCT status. Over the past two years the GCT system has undergone detailed testing and its performance is well understood. The GCT design provides for buffers at the inputs to the GCT which have been used to inject energy depositions corresponding to electrons and jets and test the GCT functionality by comparing the GCT output with that of simulation. Monte Carlo events simulating the decay of Higgs particles and other processes have been used to validate the performance of the GCT. The GCT has also been commissioned with the other components of the Level-1 trigger chain in cosmicray muon runs. Results from these studies are presented.

The Serenity-S1 is a Xilinx Virtex Ultrascale+ based Advanced Telecommunications Computing Architecture (ATCA) processing blade that has been optimised for production. It incorporates many developments from the Serenity-A and Serenity-Z prototype cards and, where possible, adopts solutions being used across CERN. It also uses many new parts because commonly used parts have disappeared from the market during the semiconductor crisis, with only some returning. Improvements to simplify manufacture, the performance of new components, some of the more difficult aspects of procurement, the performance of production-grade Samtec 25\,Gb/s optical firefly parts, and issues with the rack cooling infrastructure are discussed.

We have designed two different X-ray pixel array readout Integrated Circuits for silicon pixel detectors operating between 4 keV and 25 keV. The first allows full readout of the deposited charge for each X-ray photon and is intended for imaging X-ray spectroscopy. The second is a photon counting device capable of very high rates (1 MHz per pixel) but without energy resolution. This paper compares the architectures of these two detectors and presents experimental data from complete bump-bonded devices. These detectors have many applications from X-ray diffraction to material inspection and satellite based X-ray imaging.

A demonstrator for the CMS Level-1 calorimeter trigger system has been designed, manufactured, tested and a time-multiplexed trigger implemented. The prototype card uses the AMC double width form factor, 5Gb/s links and a Xilinx XC5VTX150T or XC5VTX240T FPGA. A possible implementation of such a trigger architecture in CMS is described.

The CMS Silicon Tracker Front-End Driver (FED) is a 9U 400mm VME64x card which processes the raw data generated within the Silicon Tracker by the APV25 readout ASICs. The processed, zero-suppressed, data is then sent to the Data Acquisition System (DAQ). The first 2 FEDs were made at the beginning of 2003 and since then a further 15 FEDs of this type (FEDv1) have been manufactured. All hardware modifications to the FEDv1 design have now been completed and a new iteration of the board produced, called the FEDv2, which is expected to be the final version. The firmware and software development is close to completion. The performance of a FED in the laboratory is presented.

The front end driver is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker signals transmitted by the APV25 analogue pipeline ASICs. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GBytes/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS DAQ system using the S-LINK64 protocol at a maximum rate of 400 Mbytes/sec. All data processing algorithms on the FED are executed in large on-board FPGAs. Results on the design, performance, testing and quality control of the FED are presented and discussed.

CERN has made public a comprehensive plan for upgrading the LHC proton-proton accelerator to provide increased luminosity commonly referred to as Super LHC (SLHC) [1]. The plan envisages two phases of upgrades during which the LHC luminosity increases gradually to reach between 6-7×10 34 cm -2 sec -1 . Over the past year, CMS has responded with a series of workshops and studies which have defined the roadmap for upgrading the experiment to cope with the SLHC environment. Increased luminosity will result in increased backgrounds and challenges for CMS and a major part of the CMS upgrade plan is a new Level-1 Trigger (L1T) system which will be able to cope with the high background environment at the SLHC. Two major CMS milestones will define the evolution of the CMS trigger upgrades: The change of the Hadronic Calorimeter electronics during phase-I and the introduction of the track trigger during phase-II. This paper outlines alternative designs for a new trigger system and the consequences for cost, latency, complexity and flexibility. In particular, it looks at how the trigger geometry of CMS could be mapped onto the latest generation of hardware while remaining backwards compatible with current infrastructure. A separate paper presented at this conference [2] looks at what could be possible if large parts of the trigger system were changed, or additional hardware added to create a time multiplexed trigger system.

The CMS Level-1 calorimeter trigger is being upgraded in two stages to maintain performance as the LHC increases pile-up and instantaneous luminosity in its second run. In the first stage, improved algorithms including event-by-event pile-up corrections are used. New algorithms for heavy ion running have also been developed. In the second stage, higher granularity inputs and a time-multiplexed approach allow for improved position and energy resolution. Data processing in both stages of the upgrade is performed with new, Xilinx Virtex-7 based AMC cards.

The CMS collaboration is preparing a major upgrade of its detector, so it can operate during the high luminosity run of the LHC from 2026. The upgraded tracker electronics will reconstruct the trajectories of charged particles within a latency of a few microseconds, so that they can be used by the level-1 trigger. An emulation framework, CIDAF, has been developed to provide a reference for a proposed FPGA-based implementation of this track finder, which employs a Time-Multiplexed (TM) technique for data processing.

The performance of the latest prototype of the radiation hard front end chip to be used by the CMS collaboration for analogue readout of the microstrip tracker has been evaluated with a silicon microstrip detector in a beam at CERN. The circuit, developed by the RD20 collaboration, consists of 128 channels of amplifier, pipeline memory, analogue signal processor and a serial multiplexer. As a result of these studies improvements in the circuit design have been devised which will be implemented in the next version.

The Front-End Driver (FED) is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker. The FED was designed to maximise the number of channels that could be processed on a single 9U board and has a mixture of optical, analogue (96 ADC channels) and digital, Field Programmable Gate Array (FPGA), components. Nevertheless, a total of 440 FED boards are required to readout the entire tracker. Nearly 20 full-scale prototype 9U FED boards have been produced to date. This paper concentrates on the issues of the large-scale manufacture and assembly of PCBs. It also discusses the issues of production testing of such large and complex electronic cards.

The CMS Global Calorimeter Trigger (GCT) uses data from the CMS calorimeters to compute a number kinematical quantities which characterize the LHC event. The GTC output is used by the Global Trigger (GT) along with data from the Global Muon Trigger (GMT) to produce the Level-1 Accept (L1A) decision. The design for the current GCT system commenced early in 2006. After a rapid development phase all the different GCT components have been produced and a large fraction of them have been installed at the CMS electronics cavern (USC-55). There the GCT system has been under test since March 2007. This paper reports results from tests which took place at the USC-55. Initial tests aimed to test the integrity of the GCT data and establish that the proper synchronization had been achieved both internally within GCT as well as with the Regional Calorimeter Trigger (RCT) which provides the GCT input data and with GT which receives the GCT results. After synchronization and data integrity had been established, Monte Carlo Events with electrons in the final state were injected at the GCT inputs and were propagated to the GCT outputs. The GCT output was compared with the predictions of the GCT emulator model in the CMS Monte Carlo and were found to be identical.

A high resolution, direct-digital detector system based upon a 2-D silicon microstrip sensor has been designed, built and is undergoing evaluation for applications in dentistry and mammography. The sensor parameters and image requirements were selected using Monte Carlo simulations. Sensors selected for evaluation have a strip pitch of 50 /spl mu/m on the p-side and 80 /spl mu/m on the n-side. Front-end electronics and data acquisition are based on the APV6 chip and were adapted from systems used at CERN for high-energy physics experiments. The APV6 chip is not self-triggering so data acquisition is done at a fixed trigger rate. This paper describes the mammographic evaluation of the double sided microstrip sensor. Raw data correction procedures were implemented to remove the effects of dead strips and non-uniform response. Standard test objects (TORMAX) were used to determine limiting spatial resolution and detectability. MTFs were determined using the edge response. The results indicate that the spatial resolution of the sensor can achieve at least 6 1p/mm with detectability performance comparable to a mammographic film/screen and amorphous silicon array. Due to the operational characteristics of the data acquisition system conventional dose estimates were not possible; instead image quality was compared on an event per pixel basis.

2D silicon strip sensors using particle physics readout technology have been evaluated as mammographic detectors. Two different versions of the APV series of front-end electronics were used that provided different noise levels. The sensors were evaluated using a typical mammography X-ray spectrum. The spatial resolution was evaluated using line pair test patterns and the modulation transfer function (MTF) was measured using the Edge Response Function. Low contrast performance was measured using the TOR(MAX) test object. Limiting spatial resolution of 52μm was obtained and an MTF value of 0.1 at 16lp/mm. The low contrast performance was estimated from 250, 500μm and 6mm diameter objects and was found to be 11.5%, 7% and better than 3.8%, respectively.

A 9U 400mm VME FED Tester card (FT) has been designed for evaluation and production testing of the CMS silicon microstrip tracker Front End Driver (FED). The FT is designed to simulate both the tracker analogue optical signals and the trigger digital signals required by a FED. Each FT can drive up to 24 FED optical input channels. The internal logic of the FT is based on large FPGAs which employ fast digital logic, digital clock managers and memories. Test patterns and real tracker data can be loaded via VME to the memories. DACs operating at 40MHz convert the data to analogue form and drive the on-board CMS tracker Analogue-Opto-Hybrids (AOH) to convert the data to analogue optical format. Hence, they are identical to the signals produced by the CMS tracker. The FT either transmits the clock and trigger information directly to a FED or to the CMS Trigger and Timing Control (TTC) system. Four such cards will be used to fully test a FED. One FT prototype has been manufactured and is currently being used to evaluate the CMS tracker FED. This paper describes the FED Tester design and architecture.

The Compact Muon Solenoid (CMS) experiment is currently installing upgrades to their Calorimeter Trigger for LHC Run 2 to ensure that the trigger thresholds can stay low, and physics data collection will not be compromised. The electronics will be upgraded in two stages. Stage-1 for 2015 will upgrade some electronics and links from copper to optical in the existing calorimeter trigger so that the algorithms can be improved and we do not lose valuable data before stage-2 can be fully installed by 2016. Stage-2 will fully replace the calorimeter trigger at CMS with a micro-TCA and optical link system. It requires that the updates to the calorimeter back-ends, the source of the trigger primitives, be completed. The new system's boards will utilize Xilinx Virtex-7 FPGAs and have hundreds of high-speed links operating at up to 10 Gbps to maximize data throughput. The integration, commissioning, and installation of stage-1 in 2015 will be described, as well as the integration and parallel installation of the stage-2 in 2015, for a fully upgraded CMS calorimeter trigger in operation by 2016.

This paper presents the test results of a prototype asynchronous hybrid pixel amplifier array chip, the PAC2, which is primarily intended for time resolved X-ray diffraction experiments, where the ability to provide time and spatial resolution in high fluxes is particularly important. The chip consists of an 8 × 8 array of 300 × 300 μm2 pixels, fabricated in 1.5 μm CMOS technology. Individual PAC2 amplifiers show an equivalent noise charge performance of less than 211 electrons r.m.s., with pixel to pixel comparator offset variations of 110 electrons r.m.s. The lower energy limit for X-ray detection can be as low as 4 keV, and results are presented from a prototype PAC2/silicon detector set-up which demonstrate close to 100% detection efficiency for 5.9 keV 55Fe X-rays.

Simulated and experimental results are presented from a silicon X-ray pixel detector which is bump bonded to a PAC5 pixel array of read-out electronics. When coupled to a matching, fully depleted silicon detector the pre-amplifier is observed to have a linear response up to 80 keV, and a pulse height resolution of around 1 keV FWHM over the range 13–60 keV. The Monte-Carlo N-Particle code has been used to simulate the detector response under illumination from a variety of energies. The excellent agreement observed between simulation and experiment illustrates the predictive abilities of such packages.

Abstract Modules of a photon counting pixelated silicon X-ray detector have been built and tested. The modules have a uniform pixel size of 150×150 μm over a silicon detector of 448×64 pixels. The detector is solder bump bonded to readout chips and then onto a molybdenum cooling substrate. Several modules have been built and images obtained with X-rays sources. The detectors work at 200 k photons per second per pixel giving a module counting rate of 6×10 9 photons per second. The modules are designed to be tiled to create larger arrays. The paper shows images obtained from the modules and describes a detector problem caused by adjacent pixels being shorted together.

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC).A crucial component of this upgrade will be the ability to reconstruct within a few microseconds all charged particle tracks with transverse momentum above 3 GeV, so they can be used in the Level-1 trigger decision.A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform followed by a track fitting based on the linear regression technique.A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters.It successfully operates on one eighth of the tracker solid angle at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying latency constraints.The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.

The I-Imas (Intelligent Imaging Sensors) is an EU project whose objective is to design and develop intelligent imaging sensors and evaluate their use within an adaptive medical imaging system specifically tailored to Mammography and Dental Radiology. The system will employ an in line scanning technology approach and proposes the use of CMOS active pixels sensors. The I-Imas sensor will have the capability of processing the data on every pixel and be able to dynamically respond in real time to changing conditions during imaging recording. The result will be to minimise the radiation exposure to areas of low diagnostic information content while extracting the highest diagnostic information from region of high interest. The first phase of the I-Imas project deals with the characterisation of the key features in a medical image that carry the highest content of diagnostic information. With this objective in mind an End-Users Survey has been carried out. We have been distributed a questionnaire to experts in the field of mammography and dental radiology (the dental radiology results will be presented elsewhere): medical physicists, radiologists, radiographers and dentists. From this survey we have collected information about the most useful specifications to be implemented in the I-Imas imaging system. This paper discusses the results from the End-Users survey and considers design implications for the I-Imas sensors