Ennio Monteil

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

The ternary phase diagram of the A1-Ga-Sb system was calculated in the whole domain of compositions, on the basis of a simple solution model. Comparison was made with published liquidus and solidus data, with our LPE growth experiments in the Ga corner and with our results of Bridgman growth from Sb rich liquid solutions. The simple solution model appeared quite satisfactory. It was adequate to describe the whole system as well as the limiting III–V binaries, and remove uncertainties resulting from the scattering of the experimental data. The phase diagram calculations were then applied to solution growth of Ga1-x A1xSb solid solutions, to predict the composition profiles of the grown solid and the thermal conditions of uniform growth.

A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. The sensor leakage current is compensated by the same feedback network. A track-and-latch voltage comparator is adopted for the hit discrimination. The hit generation is synchronized with a 40 MHz clock, minimizing time-walk issues in the time-stamp assignment. Fast ToT charge encoding up to 8-bit resolution can be retrieved at the pixel level exploiting a high-frequency self-generated clock signal. This is obtained by turning the latch into a voltage-controlled oscillator (VCO) using asynchronous logic. Pixel-to-pixel threshold variations are compensated by means of an autozeroed scheme, thus avoiding the need of a on-pixel D/A converter. An array of 8 × 8 cells with 50 μm × 50 μm pixel size has been prototyped. Design specifications, implementation and test results are discussed.

Conductance, photoconductivity and free lifetime of charge carriers in EuO thin films have been measured between 4°K and 400°K. The anomalous behaviour of conductance below 70°K in a lightly unintentionally doped sample is due to the simultaneous variation of mobility and concentration of the charge carriers. La conductivité, photoconductivité et le temps de vie des porteurs dans des couches minces de EuO ont été mesurés entre 4 et 300°K. Le comportement anormal de la conductivité au dessous de 70°K dans un échantillon légèrement dopé est du à la variation simultanée de la mobilité et de la concentration des porteurs.

Test beam results obtained with 3D pixel sensors bump-bonded to the RD53A prototype readout ASIC are reported. Sensors from FBK Italy and IMB-CNM (Spain) have been tested before and after proton-irradiation to an equivalent fluence of about 1 × 1016 ≠cm-2 (1 MeV equivalent neutrons). This is the first time that one single collecting electrode fine pitch 3D sensors are irradiated up to such fluence bump-bonded to a fine pitch ASIC. The preliminary analysis of the collected data shows no degradation on the hit detection efficiencies of the tested sensors after high energy proton irradiation, demonstrating the excellent radiation tolerance of the 3D pixel sensors. Thus, they will be excellent candidates for the extreme radiation environment at the innermost layers of the HL-LHC experiments.

This work describes the design, in 65 nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC . Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to several hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

Results obtained with 3D columnar pixel sensors bump-bonded to the RD53A prototype readout chip are reported. The interconnected modules have been tested in a hadron beam before and after irradiation to a fluence of about 1×1016 neq cm−2 (1 MeV equivalent neutrons). All presented results are part of the CMS R&D activities in view of the pixel detector upgrade for the High Luminosity phase of the LHC at CERN (HL-LHC) . A preliminary analysis of the collected data shows hit detection efficiencies around 97% measured after proton irradiation.

The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

Due to the large expected instantaneous luminosity, the future HL-LHC upgrade sets strong requirements on the radiation hardness of the CMS detector Inner Tracker. Sensors based on 3D pixel technology, with its superior radiation tolerance, comply with these extreme conditions. A full study and characterization of pixelated 3D sensors fabricated by FBK is presented here. The sensors were bump-bonded to RD53A readout chips and measured at several CERN SPS test beams. Results on charge collection and efficiency, for both non-irradiated and irradiated up to 1016 neq/cm2 samples, are presented. Two main studies are described: in the first the behaviour of the sensor is qualified as a function of irradiation, while kept under identical conditions; in the second the response is measured under typical operating conditions.

This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

The comparison of optical absorption with photoconductivity with left and right circularly polarized light versus temperature, shows similar behaviours. The transition responsible for photoconductivity has been assigned to a 4f-5d transition. Arguments are proposed to explain the relation between absorption which occurs between the 4f correlated levels and the 5d levels more delocalized and photoconductivity which has the same optical cause but whose electron is delocalized in a conduction band. La comparaison de la variation thermique de l'absorption optique avec la photoconductibilité en lumière polarisée circulairement gauche et droite montre des comportements analogues. La transition responsible de la photoconductibilité parait être une transition 4f-5d. On propose des arguments pour expliquer la relation entre l'absorption, qui a lieu entre les niveaux 4f et les niveaux 5d plus délocalisés, et la photoconductibilité qui a la même origine optique, mais dont l'électron est délocalisée dans une bande de conduction.

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm 2 ) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades.It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes.The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . ENC value is below 100 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> for an input capacitance of 50 fF and in-time threshold below 1000 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> . Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

physica status solidi (b)Volume 21, Issue 1 p. K31-K34 Short Note Diffusion and Solubility in Gallium Antimonide J. Bougnot, J. Bougnot Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this authorE. Monteil, E. Monteil Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this authorC. Llinares, C. Llinares Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this author J. Bougnot, J. Bougnot Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this authorE. Monteil, E. Monteil Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this authorC. Llinares, C. Llinares Centre d'Études d'Électronique des Solides, associé au CNRS, Faculté des Sciences, MontpellierSearch for more papers by this author First published: 1967 https://doi.org/10.1002/pssb.19670210152Citations: 5AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Citing Literature Volume21, Issue11967Pages K31-K34 RelatedInformation

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments.This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications.It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS.The prototype is composed of a matrix of 64×64 pixels with 50 µm × 50 µm cells featuring a compact design, low-noise and low-power performance.The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators.Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e -RMS for 50 fF input capacitance), below 5 µW/pixel power consumption, linear charge measurements up to 30 ke -input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel.A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm 2 hit rate, 1 MHz trigger rate and 12.5 µs trigger latency at HL-LHC.Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration.The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions.All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs.Bias currents and voltages can be monitored by a 12-bit ADC.A bandgap voltage reference circuit provides a stable reference voltage for all these blocks.The readout of triggered data is based on replicated FIFOs placed at the chip periphery.Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer.Triggerless and debug operating modes are also supported.Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions.The digital I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers.All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond.The CHIPIX65 demonstrator was submitted for fabrication on July 2016.It was

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC.The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments.Some details on the improvements implemented in the analog front-ends are provided in the paper.

The question of whether it is permissible and appropriate for arbitral tribunals to grant interim relief ex parte, like national courts around the globe do, was the subject of heated controversy in the context of the discussions leading up to the 2006 revision of the UNCITRAL Model Law. The compromise solution ultimately included in the Model Law did not attract much praise and was only adopted in a few jurisdictions. To a few notable exceptions, arbitration laws and rules remain silent on the issue. While the topic fell out of fashion for the past 15 years, it may be back in the spotlight in the context of emergency arbitration procedures. In this chapter, the authors (i) analyse the arguments in favour and against arbitral ex parte interim relief, (ii) examine how such relief has been addressed in the main arbitration rules and national arbitration laws, and (iii) question the opportunity of ex parte emergency arbitration.

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and large pixel chip size (~2×2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high hit rate (3 GHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 μs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

The High Luminosity upgrade of the CERN Large Hadron Collider (HL–LHC) calls for an upgrade of the CMS tracker detector to cope with the increased radiation levels while maintaining the excellent performance of the existing detector. Specifically, new high-radiation tolerant solid-state pixel sensors, capable of surviving irradiation fluences up to 1.9×1016neq/cm2 at 3 cm from the interaction point, need to be developed. For this purpose an R&D program involving different vendors have been pursued, aiming at the development of thin n-in-p type pixel sensors. The R&D covers both planar (manufactured by Fondazione Bruno Kessler, FBK; Hamamatsu Photonics, HPK and LFoundry) and single-sided 3D columnar (manufactured by FBK and Centro Nacional de Microelectronica, CNM) pixel devices. The target active thickness is 150μm while two different pixel cell dimensions are currently investigated (25 × 100 and 50×50μm2). Sensors presented in this article have been bump-bonded to the RD53A readout chip (ROC), the first prototype towards the development of a ROC to be employed during HL–LHC operation. Test beam studies, both of thin planar and 3D devices, have been performed by the CMS collaboration at the CERN, DESY and Fermilab test beam facilities. Results of modules performance before and after irradiation (up to 2.4×1016neq/cm2) are presented in this article.

The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout chips, both in terms of performances and reliability. To face these challenges, the use of a more downscaled CMOS technology compared to previous projects is necessary. The CERN RD53 collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology and to develop tools and frameworks which will help to design future pixel detectors. This paper gives a short overview of the RD53 collaboration activities and describes some examples of recent developments.

An innovative synchronous analog front-end for pixel detectors at HL-LHC has been designed. 600 Mrad TID irradiation at -20°C has been performed. Measurement results are presented and discussed.

The High Luminosity upgrade of the CERN LHC collider (HL-LHC) demands for a new, highradiation tolerant solid-state pixel sensor capable of surviving fluencies up to a few 10 16 n eq /cm 2 at ∼ 3 cm from the interaction point.To this extent the INFN ATLAS-CMS joint research activity, in collaboration with Fondazione Bruno Kessler (FBK), is aiming at the development of thin n-in-p type pixel sensors for the HL-LHC.The R&D covers both planar and single-sided 3D columnar pixel devices made with the Si-Si Direct Wafer Bonding technique, which allows for the production of sensors with 100 µm and 130 µm active thickness for planar sensors, and 130 µm for 3D sensors, the thinnest ones ever produced so far.Prototypes of hybrid modules, bumpbonded to the RD53A readout chip, have been tested on beam.First results on their performance before and after irradiation are presented.

In recent years the application of biostratigraphy to hydrocarbon exploration and development has become increasingly important both scientifically and economically. The demand for higher stratigraphical resolution in field development studies has resulted in the utilization of new approaches. However, in under-explored areas with little reliable primary biostratigraphical data, conventional methods using relatively coarse biozonations still have relevance. The aim of this volume is to encourage an exchange of ideas and to seed new research initiatives particularly within integrated multidisciplinary teams. The papers are divided into four main themes which cover a broad range of modern applications of biostratigraphy. The first three themes are: UK North Sea field development; outcrop analogues; and international exploration and development. The final section discusses new methodologies, such as the application of correspondence analysis and multivariate correlation of wells, and palynological processing techniques applicable to the wellsite.

An apparatus to obtain weak and high field electroreflectance spectra of the E0 transition of uniaxially stressed germanium down to 10 K is described. The electric field is applied to a Schottky barrier Ge-Cu2S. Two typical sets of weak and high field spectra are reported.