C. Foudas

Exclusive rho^0 electroproduction at HERA has been studied with the ZEUS detector using 120 pb^{-1} of integrated luminosity collected during 1996-2000. The analysis was carried out in the kinematic range of photon virtuality 2 < Q^2 < 160 GeV$^2, and gamma^* p centre-of-mass energy 32 < W < 180 GeV. The results include the Q^2 and W dependence of the gamma^* p --> rho^0 p cross section and the distribution of the squared-four-momentum transfer to the proton. The helicity analysis of the decay-matrix elements of the rho^0 was used to study the ratio of the gamma^* p cross section for longitudinal and transverse photon as a function of Q^2 and W. Finally, an effective Pomeron trajectory was extracted. The results are compared to various theoretical predictions.

The design of the ZEUS Calorimeter First Level Trigger (CFLT) is presented. The CFLT utilizes a pipelined architecture to provide trigger data for a Global First Level Trigger decision 5 μs after each beam crossing, occurring every 96 ns. The charges from 13 K phototubes are summed into 1792 trigger tower pulseheights which are digitized by flash ADCs. The digital values are linearized, stored and used for sums and pattern tests. Summary data is forwarded to the Global First Level Trigger for each crossing 2 μs after the crossing occurred. The CFLT determines the total energy, the total transverse energy, the missing energy, and the energy and number of isolated electrons and muons. It also provides information on the electromagnetic and hadronic energy deposited in various regions of the calorimeter. The CFLT has kept the experimental trigger rate below ≈ 200 Hz at the highest luminosity experienced at HERA. Performance studies suggest that the CFLT will keep the trigger rate below 1 kHz against a rate of proton-beam gas interactions on the order of the 100 kHz expected at design luminosity.

The front end driver (FED), is a 9U 400 mm VME64x card designed for reading out the compact muon solenoid (CMS), silicon tracker signals transmitted by the APV25 analogue pipeline application specific integrated circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board field programmable gate arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed

The increase of luminosity expected by LHC during Phase1 will impose tighter constraints for rate reduction in order to maintain high efficiency in the CMS Level1 trigger system. The TwinMux system is the early layer of the muon barrel region that concentrates the information from different subdetectors: Drift Tubes, Resistive Plate Chambers and Outer Hadron Calorimeter. It arranges the slow optical trigger links from the detector chambers into faster links (10 Gbps) that are sent in multiple copies to the track finders. Results from collision runs, that confirm the satisfactory operation of the trigger system up to the output of the barrel track finder, will be shown.

Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was performed in two stages, with the first running in 2015 for proton and heavy ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb−1 of data since the start of the Run II of the Large Hadron Collider (LHC). The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the μTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger processors can be expanded according to the physics needs of CMS. Sophisticated and innovative algorithms are now the core of the first decision layer of the experiment. The system has been able to adapt to the outstanding performance of the LHC, which ran with an instantaneous luminosity well above design. The performance of the system for single physics objects are presented along with the optimizations foreseen to maintain the thresholds for the harsher conditions expected during the LHC Run II and Run III periods.

An alternative design for the CMS Global Calorimeter Trigger (GCT) is being implemented. The new design adheres to all the CMS specifications regarding interfaces and functional requirements of the trigger systems. The design is modular, compact, and utilizes proven components. Functionality has been partitioned to allow commissioning in stages corresponding to the different capabilities being made operational. The functional breakdown and hardware platform is presented and discussed. A related paper discusses the firmware required to implement the GCT functionality.

The Front End Driver (FED) is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker signals transmitted by the APV25 analogue pipeline ASICs. The signals are transmitted to each FED via 96 optical fibers at a total input rate corresponding to 3 Gbytes/s. The FED digitizes the signals and processes the data digitally by applying algorithms for pedestal and common mode noise subtraction. The input data rate is reduced using algorithms that search for clusters of hits. Only the cluster data along with trigger information of the event are transmitted to the CMS DAQ system using the SLINK-64 protocol at a maximum rate of 640 Mbytes/s. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays (FPGA). Two FED cards have been manufactured during the last quarter of 2002. Results on the performance of the FED are presented and discussed.

The Global Calorimeter Trigger (GCT) is a device which uses data from the CMS calorimeters to search for jets, produce isolated and non-isolated electron lists and compute all the transverse and missing transverse energy sums used for the Level-1 trigger decision (L1A). GCT performs these functions by receiving and processing the data from the Regional Calorimeter Trigger (RCT) and transmitting a summary to the Global Trigger (GT) which computes the L1A decision. The GCT must also transmit a copy of the RCT and GCT data to the CMS DAQ. The vast amount of data received by the GCT (230 Gb/s) as well as the necessity for data sharing required by the jet finder impose severe constrains on the GCT design. This paper presents an overview of the revised design, in particular, the algorithms, data flow and associated latency within the revised GCT.

The CMS Global Calorimeter Trigger system performs a wide-variety of calorimeter data processing functions required by the CMS Level-1 trigger.It is responsible for finding and classifying jets and tau-jets, calculating total and missing transverse energy, total transverse energy identified within jets, sorting e/γ candidates, and calculating several quantities based on forward calorimetry for minimumbias triggers.The system is based on high-speed serial optical links and large FPGAs.The system has provided CMS with calorimeter triggers during commissioning and cosmic runs throughout 2008.The performance of the system in validation tests and cosmic runs is presented here.

The first prototypes of the production version of the Front-End Driver (FED) card for the CMS silicon strip tracker are about to be manufactured. The FEDs provide the off-detector processing of the tracker readout system. They digitise and zero-suppress the multiplexed analogue optical data sent on each Level-1 trigger from the ondetector APV25 pipeline chips. This paper outlines the design and describes in detail the implementation of the 96 ADC channel, 9U VME64x form factor card. In total, 440 FEDs will be required to readout the silicon strip tracker.

A digital circuit board, employing Field Programmable Gate Array (FPGA) technology, has been built to emulate the logic of the pipeline memory of the APV25 readout circuit for the CMS Silicon Strip Tracker. The primary function of the APVE design is to prevent buffer overflows in the APV25. It will also provide information to the Front End Drivers (FEDs) to ensure synchronisation throughout the Silicon Strip Tracker. The purpose and functionality of the APVE is presented along with a prediction of the performance from simulation results.

We report on preliminary design studies of a pixel detector for CMS at the Super-LHC. The goal of these studies was to investigate the possibility of designing an inner tracker pixel detector whose data could be used for selecting events at the First Level Trigger. The detector considered consists of two layers of 20x50x10 um3 pixels at very close radial proximity from each other so that coincidences of hits between the two layers amount to a track transverse momentum (pT) cut. This cut reduces the large amount of low-momentum data expected at SLHC while keeping the tracking efficiency very high for the high pT tracks. Preliminary results on the performance of such a detector are presented.

The feasibility of achieving faster data transmission using advanced digital modulation techniques over the current CMS Tracker analog optical link is explored. The spectral efficiency of Quadrature Amplitude Modulation -Orthogonal Frequency Division Multiplexing (QAM-OFDM) makes it an attractive option for a future implementation of the readout link. An analytical method for estimating the data-rate that can be achieved using OFDM over the current optical links is described and the first theoretical results are presented.

The CMS Global Calorimeter Trigger (GCT) is the device within the Level-1 CMS calorimeter trigger system which is assigned the tasks of finding and sorting forward, central and tau-jet candidates, sorting isolated and non-isolated electron candidates and reading out all of the calorimeter trigger data. The GCT system has been installed and commissioned in the CMS underground cavern. A sophisticated software package has been developed for controlling and configuring the GCT hardware and monitoring the GCT status. Over the past two years the GCT system has undergone detailed testing and its performance is well understood. The GCT design provides for buffers at the inputs to the GCT which have been used to inject energy depositions corresponding to electrons and jets and test the GCT functionality by comparing the GCT output with that of simulation. Monte Carlo events simulating the decay of Higgs particles and other processes have been used to validate the performance of the GCT. The GCT has also been commissioned with the other components of the Level-1 trigger chain in cosmicray muon runs. Results from these studies are presented.

Abstract An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. Furthermore, it provides readout for the DT detector. The ATCA processor is based on a Xilinx XCVU13P FPGA, receives data via 10 Gbps optical links and transmits track segments via 25 Gbps optical links. The processor is instrumented with a Zynq Ultrascale+ SoM connected with an SSD which provides the necessary resources for enhanced monitoring and control information. The design of the board as well as results on its performance are presented.

A demonstrator for the CMS Level-1 calorimeter trigger system has been designed, manufactured, tested and a time-multiplexed trigger implemented. The prototype card uses the AMC double width form factor, 5Gb/s links and a Xilinx XC5VTX150T or XC5VTX240T FPGA. A possible implementation of such a trigger architecture in CMS is described.

The CMS Silicon Tracker Front-End Driver (FED) is a 9U 400mm VME64x card which processes the raw data generated within the Silicon Tracker by the APV25 readout ASICs. The processed, zero-suppressed, data is then sent to the Data Acquisition System (DAQ). The first 2 FEDs were made at the beginning of 2003 and since then a further 15 FEDs of this type (FEDv1) have been manufactured. All hardware modifications to the FEDv1 design have now been completed and a new iteration of the board produced, called the FEDv2, which is expected to be the final version. The firmware and software development is close to completion. The performance of a FED in the laboratory is presented.

The front end driver is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker signals transmitted by the APV25 analogue pipeline ASICs. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GBytes/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS DAQ system using the S-LINK64 protocol at a maximum rate of 400 Mbytes/sec. All data processing algorithms on the FED are executed in large on-board FPGAs. Results on the design, performance, testing and quality control of the FED are presented and discussed.

CERN has made public a comprehensive plan for upgrading the LHC proton-proton accelerator to provide increased luminosity commonly referred to as Super LHC (SLHC) [1]. The plan envisages two phases of upgrades during which the LHC luminosity increases gradually to reach between 6-7×10 34 cm -2 sec -1 . Over the past year, CMS has responded with a series of workshops and studies which have defined the roadmap for upgrading the experiment to cope with the SLHC environment. Increased luminosity will result in increased backgrounds and challenges for CMS and a major part of the CMS upgrade plan is a new Level-1 Trigger (L1T) system which will be able to cope with the high background environment at the SLHC. Two major CMS milestones will define the evolution of the CMS trigger upgrades: The change of the Hadronic Calorimeter electronics during phase-I and the introduction of the track trigger during phase-II. This paper outlines alternative designs for a new trigger system and the consequences for cost, latency, complexity and flexibility. In particular, it looks at how the trigger geometry of CMS could be mapped onto the latest generation of hardware while remaining backwards compatible with current infrastructure. A separate paper presented at this conference [2] looks at what could be possible if large parts of the trigger system were changed, or additional hardware added to create a time multiplexed trigger system.

The CMS Level-1 calorimeter trigger is being upgraded in two stages to maintain performance as the LHC increases pile-up and instantaneous luminosity in its second run. In the first stage, improved algorithms including event-by-event pile-up corrections are used. New algorithms for heavy ion running have also been developed. In the second stage, higher granularity inputs and a time-multiplexed approach allow for improved position and energy resolution. Data processing in both stages of the upgrade is performed with new, Xilinx Virtex-7 based AMC cards.

The design and performance of the upgraded CMS Level-1 Trigger Barrel Muon Track Finder (BMTF) is presented. Monte Carlo simulation data as well as cosmic ray data from a CMS muon detector slice test have been used to study in detail the performance of the new track finder. The design architecture is based on twelve MP7 cards each of which uses a Xilinx Virtex-7 FPGA and can receive and transmit data at 10 Gbps from 72 input and 72 output fibers. According to the CMS Trigger Upgrade TDR the BMTF receives trigger primitive data which are computed using both RPC and DT data and transmits data from a number of muon candidates to the upgraded Global Muon Trigger. Results from detailed studies of comparisons between the BMTF algorithm results and the results of a C++ emulator are also presented. The new BMTF will be commissioned for data taking in 2016.

It is expected that the LHC accelerator and experiments will undergo a luminosity upgrade which will commence after several years of running. This part of the LHC operations is referred to as Super-LHC (SLHC) and is expected to provide beams of an order of magnitude larger luminosity (1035cm-2sec-1) than the current design. Preliminary results are presented from a feasibility study for a First Level Tracking Trigger for CMS at the SLHC using the data of the inner tracking detector. As a model for these studies the current CMS pixel detector with the same pixel size and radial distances from the beam has been used. Monte Carlo studies have been performed using the full CMS simulation package (OSCAR) and the occupancy of such a detector at SLHC beam conditions has been calculated. The design of an electron trigger which uses both the calorimeter energy depositions and the pixel data to identify isolated electrons and photons has been investigated. Results on the tracker occupancy and the electron trigger performance are presented

The Front-End Driver (FED) is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker. The FED was designed to maximise the number of channels that could be processed on a single 9U board and has a mixture of optical, analogue (96 ADC channels) and digital, Field Programmable Gate Array (FPGA), components. Nevertheless, a total of 440 FED boards are required to readout the entire tracker. Nearly 20 full-scale prototype 9U FED boards have been produced to date. This paper concentrates on the issues of the large-scale manufacture and assembly of PCBs. It also discusses the issues of production testing of such large and complex electronic cards.

We report on preliminary design studies of a pixel detector for CMS at the Super-LHC. The goal of these studies was to investigate the possibility of designing an inner tracker pixel detector whose data could be used for selecting events at the First Level Trigger. The detector considered consists of two layers of 20x50x10 um3 pixels at very close radial proximity from each other so that coincidences of hits between the two layers amount to a track transverse momentum (pT) cut. This cut reduces the large amount of low-momentum data expected at SLHC while keeping the tracking efficiency very high for the high pT tracks. Preliminary results on the performance of such a detector are presented.

The potential application of advanced digital communication schemes in a future upgrade of the CMS Tracker readout optical links is currently being investigated at CERN. We show experimentally that multi-Gbit/s data rates are possible over the current 40 MSamples/s analog optical links by employing techniques similar to those used in ADSL. The concept involves using one or more digitally-modulated sinusoidal carriers in order to make efficient use of the available bandwidth.

A new trigger component based on the micro-TeleCommunications Architecture (μTCA) standard is being developed for the Compact Muon Solenoid (CMS) Global Calorimeter Trigger (GCT). The new system is designed to handle the exchange of data between the GCT and the Global Muon Trigger and is called the GCT Muon and Quiet Bit System. It consists of a uTCA crate with a custom backplane instrumented with several Matrix processor cards, which use a Xilinx Virtex-5 FPGA and an M21141 72x72 cross-point switch. We discuss the development and use of the various communication systems available for the Matrix processor. Given the nature of the Virtex-5 FPGAs used as the basis of the design, there are several communication protocols available. In this paper we focus on the use of PCI express and Gigabit Ethernet UDP/IP using the built-in Virtex-5 interfaces, and TCP/IP and IPMB via an NXP microcontroller interface on the Matrix board itself. The use of these interfaces for slow control of the board and fast Data AcQuisition (DAQ) are discussed in terms of available bandwidth and resource usage. Furthermore we discuss the implications of the use of such industry-standard interfaces as a replacement for more traditional simplex busses such as VME. To that end we outline the development of a new Hardware Abstraction Layer (HAL) with built-in overlapped I/O and one possible serial bus architecture providing a metastability-tolerant interface and auto-discovery for ease of use.

The CMS Global Calorimeter Trigger (GCT) uses data from the CMS calorimeters to compute a number kinematical quantities which characterize the LHC event. The GTC output is used by the Global Trigger (GT) along with data from the Global Muon Trigger (GMT) to produce the Level-1 Accept (L1A) decision. The design for the current GCT system commenced early in 2006. After a rapid development phase all the different GCT components have been produced and a large fraction of them have been installed at the CMS electronics cavern (USC-55). There the GCT system has been under test since March 2007. This paper reports results from tests which took place at the USC-55. Initial tests aimed to test the integrity of the GCT data and establish that the proper synchronization had been achieved both internally within GCT as well as with the Regional Calorimeter Trigger (RCT) which provides the GCT input data and with GT which receives the GCT results. After synchronization and data integrity had been established, Monte Carlo Events with electrons in the final state were injected at the GCT inputs and were propagated to the GCT outputs. The GCT output was compared with the predictions of the GCT emulator model in the CMS Monte Carlo and were found to be identical.

We report recent work on the design of a pixel detector for CMS at the Super-LHC. This work builds on previous studies of a tracking detector capable of providing track stubs to be used in the Level-1 Trigger (L1T). We now focus on the use of two ‘superlayers’ of tracking; each comprising a pair of pixel sensors with 50×50×50μm pitch (z×φ×r) separated by a few millimetres. Preliminary work on track reconstruction in Field Programmable Gate Arrays (FPGAs) is also presented.

This document specifies the functionality which will be required of the final Front End Drivers (FEDs) for the Tracker, and explains the motivation behind each of these requirements. Furthermore, it lists all the input/output signals which these FEDs must deal with. Also discussed is the issue of what subset of this functionality will be in the first version of the final FED (FF1), which will be used for rod/petal testing in 2002. Not addressed in this document are details of the implementation. This will be described in a separate ‘FED Specifications’ document.

It is expected that the LHC accelerator and experiments will undergo a luminosity upgrade which will commence after several years of running. This part of the LHC operations is referred to as Super-LHC (SLHC) and is expected to provide beams of an order of magnitude larger luminosity (10 35 cm -2 sec -1 ) than the current design. Preliminary results are presented from a feasibility study for a First Level Tracking Trigger for CMS at the SLHC using the data of the inner tracking detector. As a model for these studies the current CMS pixel detector with the same pixel size and radial distances from the beam has been used. Monte Carlo studies have been performed using the full CMS simulation package (OSCAR) and the occupancy of such a detector at SLHC beam conditions has been calculated. The design of an electron trigger which uses both the calorimeter energy depositions and the pixel data to identify isolated electrons and photons has been investigated. Results on the tracker occupancy and the electron trigger performance are presented.

A 9U 400mm VME FED Tester card (FT) has been designed for evaluation and production testing of the CMS silicon microstrip tracker Front End Driver (FED). The FT is designed to simulate both the tracker analogue optical signals and the trigger digital signals required by a FED. Each FT can drive up to 24 FED optical input channels. The internal logic of the FT is based on large FPGAs which employ fast digital logic, digital clock managers and memories. Test patterns and real tracker data can be loaded via VME to the memories. DACs operating at 40MHz convert the data to analogue form and drive the on-board CMS tracker Analogue-Opto-Hybrids (AOH) to convert the data to analogue optical format. Hence, they are identical to the signals produced by the CMS tracker. The FT either transmits the clock and trigger information directly to a FED or to the CMS Trigger and Timing Control (TTC) system. Four such cards will be used to fully test a FED. One FT prototype has been manufactured and is currently being used to evaluate the CMS tracker FED. This paper describes the FED Tester design and architecture.

To maintain the excellent performance of the LHC during its Run-1 also in Run-2, the Level-1 Trigger of the Compact Muon Solenoid experiment underwent a significant upgrade.One part of this upgrade was the re-organisation of the muon trigger path from a subsystem-centric view in which hits in the drift tubes, the cathode strip chambers, and the resistive plate chambers were treated separately in dedicated track-finding systems, to one in which complementary detector systems for a given region (barrel, overlap, and endcap) are merged already at the track-finding level.This also required the development of a new system to sort as well as cancel-out the muon tracks found by each system.An overview will be given of the new track-finder system for the barrel region, the Barrel Muon Track Finder (BMTF) as well as the cancel-out and sorting layer, the upgraded Global Muon Trigger (µGMT).While the BMTF improves on the proven and well-tested algorithms used in the Drift Tube Track Finder during Run-1, the µGMT is an almost complete re-development due to the re-organisation of the underlying systems from complementary track finders to regional track finders.Additionally, the µGMT can calculate a muon isolation using energy information that will be received from the calorimeter trigger in the future.This information is added to the muon objects forwarded to the Global Trigger.Finally, first results of the muon trigger performance including the barrel region are shown.Both the trigger efficiency and the rate reduction show satisfactory performance, with improvements planned for the near future.

The potential application of advanced digital communication schemes in a future upgrade of the CMS Tracker readout optical links is currently being investigated at CERN. We show experimentally that multi-Gbit/s data rates are possible over the current 40 MSamples/s analog optical links by employing techniques similar to those used in ADSL. The concept involves using one or more digitally-modulated sinusoidal carriers in order to make efficient use of the available bandwidth.

The Level-1 trigger of the CMS experiment at CERN has been designed to select proton-proton interactions whose final state includes signatures of new physics in the form of high transverse energy electrons, photons, jets, or high missing transverse energy. The Level-1 trigger system process data in a pipeline fashion at a rate of 40 MHz, has a design latency of 128 bunch crossings and an output rate of 100 KHz. The design of this system is presented with emphasis on the calorimeter triggers. After a long period of testing and validation of its performance the Level-1 trigger system has been installed and commissioned at the CMS experiment at CERN. Cosmic ray data and Monte Carlo events have been used to compare the actual performance of the trigger with expectations from off-line emulation models. Results from these studies are presented here. The limitations of this system to cope with future luminosity upgrades of the LHC, the Super-LHC, are discussed. The current CMS plan for a new CMS Level-1 trigger system at the Super-LHC is presented. The center point of the new system is a Level-1 tracking trigger which uses data from a new CMS silicon tracking detector.

The Barrel Muon Track finder of the CMS experiment at the Large Hadron Collider uses custom processors to identify muons and measure their momenta in the central region of the CMS detector. An upgrade of the L1 tracking algorithm is presented, featuring a Kalman Filter in FPGAs, implemented using High Level Synthesis tools. The matrix operations are mapped to the DSP cores reducing resource utilization to a level that allows the new algorithm to fit in the same FPGA as the legacy one, thus enabling studies during nominal CMS data taking. The algorithm performance has been verified in CMS collisions during 2018 operations. The algorithm is also proposed for standalone muon tracking at the High Luminosity LHC. The algorithm development is complemented by ATCA processor R&D featuring a large ZYNQ Ultrascale+ SoC with high speed optical links.

The CMS Silicon Tracker comprises a complicated set of hardware and software components that have been thoroughly tested at CERN before final integration of the Tracker. A vertical slice of the full readout chain has been operated under near-final conditions. In the absence of the tracker front-end modules, simulated events have been created within the FED (Front End Driver) and used to test the readout reliability and efficiency of the final DAQ (Data Acquisition). The data are sent over the S-Link 64 bit links to the FRL (Fast Readout Link) modules at rates in excess of 200 MBytes/s per FED depending on setup and conditions. The current tracker DAQ is fully based on the CMS communication and acquisition tool XDAQ. This paper discusses setup and results of a vertical slice of the full Tracker final readout system comprising 2 full crates of FEDs, 30 in total, read out through 1 full crate of final FRL modules. This test is to complement previous tests done at Imperial College[3] taking them to the next level in order to prove that a complete crate of FRLs using the final DAQ system, including all subcomponents of the final system both software and hardware with the exception of the detector modules themselves, is capable of sustained readout at the desired rates and occupancy of the CMS Tracker. Simulated data are created with varying hit occupancy (1-10%) and Poisson distributed trigger rates (<200KHz) and the resulting behaviour of the system is recorded. Data illustrating the performance of the system and data readout are presented.

In order to separate the interesting physics events from the background without unmanageable deadtime, the ZEUS experiment uses a pipelined trigger and data acquisition system. One of the chief elements of the first level trigger is the Calorimeter First Level Trigger (CFLT). It provides three different categories of information to the Global First Level Trigger (GFLT): numbers of isolated electrons and muons in the calorimeter, patterns of energy deposition derived from local energy sums, and total energy, transverse energy, and missing energy deposited in the calorimeter. The CFLT has to make each step of these calculations, including digitization of the photomultiplier-tube pulse, at a rate of 96 ns in order to keep up with the pipeline. However, in order to reduce the amount of electronics, cables, and crate backplane required, the data are multiplexed in time at several points so that many elements of the system run at faster rates, up to 83 MHz. The CFLT passes trigger information to the GFLT within 2 mu s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>