¤ Open Access
Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions
This paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to proVide shallow source and drain regions and a nonuniform substrate doping profile. Onedimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFETs with channel lengths as short as 0.5μ were fabricated, and the device characteristics measured and compared with predicted values. Ibe performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. Reprintedfrom the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.]
Frontiers of silicon-on-insulator
Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.
¤ Open Access
Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.
Time-Resolved Temperature Measurement of AlGaN/GaN Electronic Devices Using Micro-Raman Spectroscopy
We report on the development of time-resolved Raman thermography to measure transient temperatures in semiconductor devices with submicrometer spatial resolution. This new technique is illustrated for AlGaN/GaN HFETs and ungated devices grown on SiC and sapphire substrates. A temporal resolution of 200 ns is demonstrated. Temperature changes rapidly within sub-200 ns after switching the devices on or off, followed by a slower change in device temperature with a time constant of ~10 and ~140 mus for AlGaN/GaN devices grown on SiC and sapphire substrates, respectively. Heat diffusion into the device substrate is also demonstrated
Measurement and modeling of self-heating in SOI nMOSFET's
Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >
SThM Temperature Mapping and Nonlinear Thermal Resistance Evolution With Bias on AlGaN/GaN HEMT Devices
Channel temperature has a strong impact on the performance of a microwave power transistor. In particular, it has a strong influence on the power gain, energetic efficiency, and reliability of the device. The thermal optimization of device geometry is therefore a key issue, together with precise measurements of temperature within the channel area. In this paper, we have used scanning thermal microscopy to perform temperature mapping, at variable dc bias points, on an AlGaN/GaN high-electron mobility transistor made on epilayers grown on silicon carbide substrate. We have analyzed the variation of the thermal resistance values, which are deduced from these measurements, with bias conditions VGS and VDS. The observed nonlinear behavior is found to be in excellent agreement with physical simulations, strongly pointing out the large variability of the extension of the dissipation area with the dc bias conditions