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Computer architecture (Page 1)

set of rules and methods that describe the functionality, organization, and implementation of computer systems

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  2. computer science » 
  3. Computer architecture
Subconcepts:
  1. Co-design
  2. Computer design
  3. Digital computer
  4. Electronic design
  5. General purpose
  6. Processor design
  7. SystemC
  8. Very long instruction word
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Papers in this category: 185 371 Current Page: 1 / 100
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DOI: 10.1109/mcom.2013.6476878
2013
Cited 847 times
Seven ways that HetNets are a cellular paradigm shift
DOI: 10.1126/science.280.5370.1716
1998
Cited 845 times
A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology
DOI: 10.5555/266800.266832
1997
Cited 844 times
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
DOI: 10.1109/mm.2010.41
2010
Cited 840 times
The GPU Computing Era
DOI: 10.1038/s41565-020-0655-z
2020
Cited 833 times
Memory devices and applications for in-memory computing
DOI: 10.1109/mdt.2005.99
2005
Cited 826 times
Æthereal Network on Chip:Concepts, Architectures, and Implementations
MAG: 1564594068
2002
Cited 825 times
Patterns of Enterprise Application Architecture
DOI: 10.1109/tie.2007.898281
2007
Cited 804 times
FPGA Design Methodology for Industrial Control Systems—A Review
DOI: 10.1109/40.755465
1999
Cited 803 times
The Alpha 21264 microprocessor
DOI: 10.1147/rd.494.0589
2005
Cited 802 times
Introduction to the Cell multiprocessor
DOI: 10.1145/130823.130824
1992
Cited 800 times
SPLASH
DOI: 10.1109/71.207593
1993
Cited 799 times
A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures
DOI: 10.1038/s41586-019-1157-8
2019
Cited 797 times
All-optical spiking neurosynaptic networks with self-learning capabilities
DOI: 10.1109/mm.2006.82
2006
Cited 796 times
The M5 Simulator: Modeling Networked Systems
DOI: 10.1109/tc.2005.134
2005
Cited 792 times
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
DOI: 10.1109/40.491460
1996
Cited 791 times
The Mips R10000 superscalar microprocessor
DOI: 10.1038/s41586-019-1677-2
2019
Cited 782 times
Towards spike-based machine intelligence with neuromorphic computing
DOI: 10.1109/12.859540
2000
Cited 780 times
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
DOI: 10.1109/icdmw.2010.172
2010
Cited 778 times
S4: Distributed Stream Computing Platform
MAG: 1504850170
1997
Cited 775 times
Modeling rational agents with a BDI-architecture
DOI: 10.1007/978-1-4302-0166-3_3
2006
Cited 773 times
Web Services Architecture
DOI: 10.17487/rfc3945
2004
Cited 765 times
Generalized Multi-Protocol Label Switching (GMPLS) Architecture
DOI: 10.1109/4.509850
1996
Cited 764 times
CACTI: an enhanced cache access and cycle time model
MAG: 2121082877
2006
Cited 762 times
The Landscape of Parallel Computing Research: A View from Berkeley
DOI: 10.1145/1345206.1345220
2008
Cited 743 times
Optimization principles and application performance evaluation of a multithreaded GPU using CUDA
DOI: 10.1109/jproc.2018.2790840
2018
Cited 743 times
Neuro-Inspired Computing With Emerging Nonvolatile Memorys
DOI: 10.1016/j.patcog.2020.107404
2020
Cited 741 times
U2-Net: Going deeper with nested U-structure for salient object detection
DOI: 10.1145/1629575.1629579
2009
Cited 736 times
The multikernel
DOI: 10.1109/32.67579
1991
Cited 735 times
The x-Kernel: an architecture for implementing network protocols
DOI: 10.1038/nmeth.2926
2014
Cited 733 times
Principles of genetic circuit design
DOI: 10.1109/cvpr42600.2020.01044
2020
Cited 728 times
Designing Network Design Spaces
DOI: 10.1145/1629575.1629589
2009
Cited 724 times
Better I/O through byte-addressable, persistent memory
DOI: 10.1007/3-540-63465-7_226
1997
Cited 722 times
VPR: a new packing, placement and routing tool for FPGA research
MAG: 3169463464
1997
Cited 717 times
Interconnection Networks: An Engineering Approach
DOI: 10.1016/s0010-4655(00)00065-5
2000
Cited 704 times
High performance computational chemistry: An overview of NWChem a distributed parallel application
DOI: 10.1145/232973.232993
1996
Cited 687 times
Exploiting choice
MAG: 1850405760
1998
Cited 683 times
Parallel Computer Architecture: A Hardware/Software Approach
DOI: 10.1145/3079856.3080254
2017
Cited 682 times
SCNN
MAG: 2962746461
2018
Cited 681 times
Efficient Neural Architecture Search via Parameters Sharing
DOI: 10.17487/rfc4838
2007
Cited 680 times
Delay-Tolerant Networking Architecture
DOI: 10.1145/1278480.1278667
2007
Cited 672 times
Thousand core chips
DOI: 10.1109/tc.1981.1675695
1981
Cited 670 times
Performance of Processor-Memory Interconnections for Multiprocessors
DOI: 10.1109/tc.1983.1676201
1983
Cited 663 times
The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer
DOI: 10.1145/1401132.1401152
2008
Cited 662 times
Scalable parallel programming with CUDA
DOI: 10.1145/1454115.1454152
2008
Cited 652 times
Mars
DOI: 10.1063/5.0005082
2020
Cited 650 times
Q<scp>uantum</scp> ESPRESSO toward the exascale
DOI: 10.1038/ncomms15199
2017
Cited 649 times
Face classification using electronic synapses
DOI: 10.1016/j.jpdc.2014.07.003
2014
Cited 648 times
Kokkos: Enabling manycore performance portability through polymorphic memory access patterns
DOI: 10.1109/tcad.2008.2010691
2009
Cited 638 times
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
DOI: 10.1098/rsta.2011.0214
2012
Cited 636 times
Underwater sensor networks: applications, advances and challenges
DOI: 10.1109/tcad.2011.2110592
2011
Cited 634 times
High-Level Synthesis for FPGAs: From Prototyping to Deployment
DOI: 10.1038/s41566-020-00754-y
2021
Cited 633 times
Photonics for artificial intelligence and neuromorphic computing
DOI: 10.17487/rfc2638
1999
Cited 632 times
A Two-bit Differentiated Services Architecture for the Internet
DOI: 10.1177/109434200001400303
2000
Cited 627 times
A Portable Programming Interface for Performance Evaluation on Modern Processors
DOI: 10.1109/ipsn.2005.1440950
2005
Cited 626 times
Telos: enabling ultra-low power wireless research
DOI: 10.1145/1356052.1356053
2008
Cited 622 times
Anatomy of high-performance matrix multiplication
DOI: 10.1145/1360612.1360617
2008
Cited 622 times
Larrabee
DOI: 10.1002/j.1460-2075.1989.tb03597.x
1989
Cited 620 times
The gene coding for the major birch pollen allergen Betv1, is highly homologous to a pea disease resistance response gene.
DOI: 10.1038/s41928-018-0103-3
2018
Cited 618 times
Organic electronics for neuromorphic computing
DOI: 10.1007/s11263-014-0788-3
2014
Cited 611 times
Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition
DOI: 10.1145/2228360.2228584
2012
Cited 609 times
Chisel
DOI: 10.1109/jetcas.2019.2910232
2019
Cited 609 times
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
DOI: 10.1109/mcom.2017.1600935
2017
Cited 602 times
Network Slicing for 5G with SDN/NFV: Concepts, Architectures, and Challenges
DOI: 10.1109/tcsi.2012.2215714
2013
Cited 601 times
TEAM: ThrEshold Adaptive Memristor Model
DOI: 10.1109/40.592312
1997
Cited 601 times
A case for intelligent RAM
DOI: 10.1021/acsnano.8b03569
2018
Cited 598 times
Deep-Learning-Enabled On-Demand Design of Chiral Metamaterials
MAG: 3143002681
1995
Cited 598 times
Digital Integrated Circuits
DOI: 10.1007/bf01205185
1993
Cited 596 times
The superblock: An effective technique for VLIW and superscalar compilation
DOI: 10.1177/1094342010391989
2011
Cited 596 times
The International Exascale Software Project roadmap
MAG: 2995746888
1988
Cited 592 times
VLSI array processors
DOI: 10.1109/mm.2003.1225959
2003
Cited 588 times
Trends and challenges in VLSI circuit reliability
MAG: 2964259004
2018
Cited 584 times
ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware
DOI: 10.1109/2.612254
1997
Cited 580 times
Baring it all to software: Raw machines
DOI: 10.3389/fnins.2019.00095
2019
Cited 576 times
Going Deeper in Spiking Neural Networks: VGG and Residual Architectures
DOI: 10.1145/360827.360844
1974
Cited 574 times
The parallel execution of DO loops
DOI: 10.1073/pnas.1604850113
2016
Cited 574 times
Convolutional networks for fast, energy-efficient neuromorphic computing
DOI: 10.1109/jproc.2015.2444094
2015
Cited 573 times
Memory and Information Processing in Neuromorphic Systems
DOI: 10.1021/ct300857j
2012
Cited 573 times
OpenMM 4: A Reusable, Extensible, Hardware Independent Library for High Performance Molecular Simulation
DOI: 10.1145/3020078.3021744
2017
Cited 573 times
FINN
DOI: 10.1145/264107.264206
1997
Cited 570 times
The SGI Origin
DOI: 10.1145/264107.264201
1997
Cited 569 times
Complexity-effective superscalar processors
DOI: 10.1038/ncomms4541
2014
Cited 567 times
Experimental demonstration of reservoir computing on a silicon photonics chip
DOI: 10.1109/82.842110
2000
Cited 563 times
Point-to-point connectivity between neuromorphic chips using address events
DOI: 10.1109/access.2018.2877890
2018
Cited 562 times
Benchmark Analysis of Representative Deep Neural Network Architectures
DOI: 10.1109/ispass.2009.4919636
2009
Cited 559 times
GARNET: A detailed on-chip network model inside a full-system simulator
DOI: 10.1109/mm.2011.89
2011
Cited 558 times
GPUs and the Future of Parallel Computing
DOI: 10.1145/2517349.2522738
2013
Cited 557 times
Naiad
DOI: 10.1080/23746149.2016.1259585
2016
Cited 557 times
Neuromorphic computing using non-volatile memory
MAG: 164384110
2010
Cited 556 times
CUDA by Example: An Introduction to General-Purpose GPU Programming
DOI: 10.21437/interspeech.2015-647
2015
Cited 553 times
A time delay neural network architecture for efficient modeling of long temporal contexts
DOI: 10.1109/54.232470
1993
Cited 549 times
Hardware-software cosynthesis for digital systems
DOI: 10.1038/nature22994
2017
Cited 548 times
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
DOI: 10.1145/343647.343776
2000
Cited 547 times
A generic architecture for on-chip packet-switched interconnections
DOI: 10.1147/rd.461.0005
2002
Cited 546 times
POWER4 system microarchitecture
DOI: 10.1109/fpga.1997.624600
2002
Cited 545 times
Garp: a MIPS processor with a reconfigurable coprocessor
DOI: 10.1038/s41467-018-04933-y
2018
Cited 544 times
Neuromorphic computing with multi-memristive synapses
DOI: 10.1038/s41467-018-04484-2
2018
Cited 544 times
Efficient and self-adaptive in-situ learning in multilayer memristor neural networks
DOI: 10.1109/cvpr.2019.00881
2019
Cited 541 times
HAQ: Hardware-Aware Automated Quantization With Mixed Precision
DOI: 10.1145/1735688.1735702
2010
Cited 540 times
The Scalable Heterogeneous Computing (SHOC) benchmark suite
MAG: 1606347560
2012
Cited 539 times
Theano: new features and speed improvements
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Papers in this category: 185 371 Current Page: 1 / 100
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